Multi-level memristor element synthesis for edge computing
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Solution Overview
Problem
Traditional Von Neumann computing architecture presents a bottleneck in time-critical systems like speech processing due to the continuous reading and writing of data between processor and memory, limiting efficiency and power consumption, especially in low-power, always-on applications such as edge computing. Additionally, analog memristors face manufacturing challenges and inconsistency in operation.
Innovation Solution
A two-terminal multi-level memristor element synthesized from binary memristors, with series-connected binary memristor portions programmable between high and low resistance states, allowing for variable multi-level resistance. This includes switching circuitry and a program control module to adjust resistance based on input data, using unary or binary coding, and dynamic element matching to compensate for manufacturing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog memristors are used to provide continuous impedance variations, then computing capability and flexibility are improved, but manufacturing consistency and operational reliability deteriorate
Solution Approach 1:
The patent segments an analog memristor into multiple binary memristor portions connected in series, where each portion can be independently programmed to HI or LO resistance states. This segmentation transforms a single complex analog device into multiple simpler binary devices, improving manufacturability and consistency while maintaining multi-level resistance capability through combinatorial switching of the segments.
2Reliability
If binary memristors are used instead of analog memristors, then manufacturing consistency is improved, but computing flexibility and multi-level resistance capability deteriorate
Solution Approach 1:
The patent merges multiple binary memristor portions in series connection to synthesize a multi-level memristor element. By combining several simple binary devices, the system achieves the functional equivalence of an analog memristor with continuous impedance variations, thereby restoring computing flexibility while maintaining the manufacturing advantages of binary devices.
Solution Approach 2:
The patent introduces a new dimension of control by programming individual binary memristor portions to different resistance states. Instead of relying on continuous analog control of a single device, the system uses discrete control of multiple devices, creating a combinatorial space of resistance values that provides multi-level capability without requiring analog precision in individual components.
3Ease of operation
If traditional Von Neumann architecture is used, then data access is simplified, but processing speed and power efficiency deteriorate due to continuous data transfer between processor and memory
Solution Approach 1:
The patent merges memory and processing functions by implementing synapse circuits where multi-level memristor elements directly perform computing operations. The memristors store weighting values and simultaneously participate in analog computing operations like multiply-accumulate, eliminating the need for separate data transfer between memory and processor, thereby improving processing speed and power efficiency.
4Device complexity
If traditional Von Neumann architecture is used, then system design is simplified, but power consumption increases due to continual reading and writing operations
Solution Approach 1:
The patent implements synapse circuits where memristor elements perform computing operations autonomously without requiring external control logic or data transfer protocols. The multi-level memristors directly compute weighted sums through analog current division, eliminating the need for traditional processor-controlled read/write operations and significantly reducing power consumption in always-on applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient, low-power operation by providing a consistent and easily manufacturable multi-level memristor element that balances power consumption, accuracy, and processing speed, suitable for synapse circuits in machine learning systems, effectively mitigating the bottlenecks in traditional computing architectures.
Implementation Method 1
binary memristor portions individually programmable between HI and LO resistance states, wherein the series-connected binary memristor portions can be programmed to provide a variable multi-level resistance between the first and second terminals
Data Source
AI summary
There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.