Multi-Level NVRAM Memory Subsystem with DRAM Cache Segmentation
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Solution Overview
Problem
Current memory subsystems face challenges in achieving a balance between cost, power consumption, and performance, particularly when transitioning from traditional DRAM to Phase-Change Memory and Switch (PCMS) technology, which exhibits higher latency and lower bandwidth, along with asymmetrical read and write capabilities.
Innovation Solution
Implementing a multi-level memory subsystem with direct non-volatile access using Non-Volatile Random Access Memory (NVRAM) that integrates PCMS with DRAM as a cache, employing address redirection tables and page cleaning processes to optimize data access and minimize write latency, and utilizing a dual-partitioned NVRAM system for efficient memory and storage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If PCMS non-volatile storage is used to replace DRAM, then cost and power consumption are improved, but access speed and bandwidth deteriorate
Solution Approach 1:
The memory system is segmented into multiple levels: volatile DRAM cache for high-speed access and non-volatile PCMS storage for persistent data. This segmentation allows the system to leverage the speed of DRAM for frequently accessed data while using the lower-power PCMS for less frequently accessed data, thus resolving the contradiction between power consumption and access speed.
Solution Approach 2:
A memory controller acts as an intermediary between the processor and the multi-level memory system. It manages data transfer between DRAM cache and PCMS storage, optimizing access patterns to minimize the performance penalty of using slower non-volatile storage while maximizing power savings.
2Ease of manufacture
If PCMS non-volatile storage is used to replace DRAM, then cost is improved, but bandwidth deteriorates
Solution Approach 1:
The storage system is segmented into high-bandwidth DRAM regions for active data processing and lower-bandwidth PCMS regions for persistent storage. This allows the system to achieve cost savings from PCMS usage while maintaining high bandwidth performance for critical data operations through the DRAM segment.
3Productivity
If direct address space mapping is implemented for non-volatile storage, then access efficiency is improved, but system complexity increases
Solution Approach 1:
The memory controller serves as an intermediary that handles the complexity of address mapping, translation, and data movement between the processor's address space and the physical multi-level memory structure. This intermediary approach enables direct access efficiency while encapsulating the system complexity within the controller rather than requiring complex changes throughout the entire system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient data access and reduced power consumption by leveraging NVRAM's low power and high read speeds, while managing write operations to maintain system performance and extend the lifespan of PCMS devices through wear leveling and page cleaning mechanisms.
Implementation Method 1
Phase-Change Memory and Switch (PCMS) is a non-volatile storage technology
Data Source
AI summary
Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.