Multi-Level Polycrystalline Semiconductor Region for RF Isolation
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Solution Overview
Problem
Conventional techniques for forming buried and non-buried high-resistivity polycrystalline semiconductor regions in bulk semiconductor substrates are either performed too early or too late in the fabrication process, disrupting the formation of integrated circuits and affecting device performance.
Innovation Solution
A bulk semiconductor structure with a multi-level polycrystalline semiconductor region, comprising buried and non-buried portions, is formed concurrently using a single module, where trench isolation regions and a monocrystalline semiconductor region are integrated to optimize the depth and position of the polycrystalline regions, allowing for simultaneous formation of first-level and second-level portions with distinct maximum depths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buried high-resistivity polycrystalline semiconductor regions are formed prior to semiconductor device formation, then harmonics and parasitic loss are reduced, but the fabrication process complexity increases and device formation is disrupted
Solution Approach 1:
The patent combines the formation of buried and non-buried polycrystalline semiconductor regions into a single simultaneous processing step using one ion implantation module, rather than performing separate processing steps at different stages of fabrication. This merging approach maintains the harmonic reduction benefits while simplifying the overall fabrication process sequence
Solution Approach 2:
The ion implantation module performs multiple functions simultaneously: it creates both buried polycrystalline regions (for harmonic reduction) and non-buried polycrystalline regions (for device isolation and performance), while also defining trench isolation regions. This multi-functionality eliminates the need for separate dedicated processing steps
2Reliability
If non-buried high-resistivity polycrystalline semiconductor regions are formed following silicide formation, then device isolation is improved, but the fabrication process time increases
Solution Approach 1:
The patent merges the formation of non-buried polycrystalline regions with the formation of buried polycrystalline regions into a single simultaneous processing step. This eliminates the sequential time penalty where non-buried regions were formed after silicide formation in separate steps
Solution Approach 2:
The patent performs preliminary ion implantation to create both buried and non-buried polycrystalline regions before subsequent device formation steps, including silicide formation. This preliminary action ensures that isolation structures are already in place to prevent contamination and performance degradation during later processing
3Manufacturing precision
If separate processing steps are used for buried and non-buried polycrystalline regions, then manufacturing precision is maintained, but productivity decreases
Solution Approach 1:
The patent uses a single ion implantation module with multiple implantation conditions (different energies, doses, and masking schemes) to create both buried and non-buried polycrystalline regions simultaneously. This maintains the precision of separate processing while achieving the throughput of combined processing
Solution Approach 2:
The patent segments the ion implantation process into multiple distinct implantation steps within a single module operation, where each implantation targets specific regions with specific parameters. This segmentation allows precise depth and concentration control for different polycrystalline regions while maintaining overall process efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a semiconductor structure that reduces harmonics and parasitic loss in RF switches and other semiconductor devices, improving the overall performance and efficiency of integrated circuits by aligning the polycrystalline regions with trench isolation structures, thus optimizing device isolation and functionality.
Implementation Method 1
a doped region can be formed within the semiconductor substrate such that the doped region has a modified crystalline structure
Implementation Method 2
Following the dopant implantation process, the doped region can be recrystallized. Recrystallization of the doped region creates a monocrystalline semiconductor region and a multi-level polycrystalline semiconductor region
Data Source
AI summary
Disclosed is a bulk semiconductor structure that includes a semiconductor substrate with a multi-level polycrystalline semiconductor region that includes one or more first-level portions (i.e., buried portions) and one or more second-level portions (i.e., non-buried portions). Each first-level portion can be within the semiconductor substrate some distance below the top surface (i.e., buried), can be aligned below a monocrystalline semiconductor region and/or a trench isolation region, and can have a first maximum depth. Each second-level portion can be within the semiconductor substrate at the top surface, can be positioned laterally adjacent to a trench isolation region, and can have a second maximum depth that is less than the first maximum depth. Also disclosed herein are method embodiments for forming the bulk semiconductor structure wherein the first-level and second-level portions of the multi-level polycrystalline semiconductor region are concurrently formed (e.g., using a single module).