Multi-level Port Translation for Deterministic Network Routing

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Solution Overview

Problem

Existing network routing technologies face challenges in accurately representing physical paths due to variations in port usage across switches and the presence of fat links, which complicates route computation and path determinism.

Innovation Solution

A multi-level port mapping scheme is employed, decoupling algorithmic route computation from physical wiring, allowing for variable fatness across links and enabling deterministic routing by translating logical or virtual port identifiers to physical output ports using translation tables.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a uniform logical port map is used for route computation, then route computation is simplified, but it cannot correctly describe actual physical paths in the network due to variations in port usage across switches

Engineering Contradiction:
Improveroute computationVSAvoidphysical path description
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent introduces virtual port identifiers as an intermediary layer between logical port identifiers and physical port identifiers. Virtual port identifiers serve as mediators that can be uniformly mapped for route computation while still accurately representing physical paths through switch-specific translation tables. This resolves the contradiction by allowing simplified uniform logical mapping while maintaining precise physical path description through the virtual port intermediary.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If physical port assignments are made to accommodate arbitrary wiring constraints, then adaptability to network topology is improved, but deterministic routing becomes difficult to ensure

Engineering Contradiction:
Improvewiring constraints accommodationVSAvoidrouting path determinism
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent pre-establishes translation tables that map virtual port identifiers to physical port identifiers for each switch during network initialization. This preliminary action ensures that regardless of arbitrary wiring constraints, the routing path can be deterministically computed using virtual port identifiers, with the actual physical port assignments being predetermined and stored in the translation tables. This resolves the contradiction by enabling both adaptability to arbitrary wiring and deterministic routing through pre-computed mappings.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If multi-level port translation is implemented to decouple logical routing from physical wiring, then routing flexibility is improved, but system complexity increases

Engineering Contradiction:
Improverouting flexibilityVSAvoidport mapping system
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the port identification system into three distinct levels: logical port identifiers for routing computation, virtual port identifiers for path representation, and physical port identifiers for actual wiring. This segmentation allows each layer to operate independently with its own translation rules, providing routing flexibility while managing complexity through clear separation of concerns. The modular structure enables flexible routing decisions at the logical layer without being constrained by physical wiring complexities.

Inventive Principle:
Principle #1Segmentation

4Measurement precision

If translation tables are used to map logical ports to physical ports, then accurate physical path representation is achieved, but memory overhead increases

Engineering Contradiction:
Improvephysical path representationVSAvoidmemory usage
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent implements translation tables locally at each switch rather than maintaining a global translation table across the entire network. Each switch maintains only the translation mappings relevant to its own ports and connections. This local quality approach reduces the overall memory overhead by distributing the translation information across multiple switches, with each switch storing only a fraction of the total translation data needed for accurate physical path representation.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250126044A1Multi-level port translation for routing in networks
Publication Date: 2025.04.17 INTEL CORP
  • US20250126044A1 patent drawing
  • US20250126044A1 patent drawing
  • US20250126044A1 patent drawing

AI summary

Examples described herein relate to performing source routing of a packet to route the packet from a source to a destination through multiple routers by specification of a path of logical port identifiers through the multiple routers. In some examples, multiple routers are to translate the logical port identifiers into physical ports based on configurations. In some examples, the path of the packet through the multiple routers is based on a topology of the routers.