Multi-Level Power Supply Wiring for Reduced Resistance
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Solution Overview
Problem
Existing semiconductor device power supply line configurations face challenges in reducing wiring resistance, particularly when connecting power supply main lines, which can prevent circuit placement and increase resistance with distance, leading to inefficiencies and larger chip sizes.
Innovation Solution
A multi-level wiring structure is implemented with power supply lines of different voltages arranged in overlapping layers, connected by regular contacts and vias in interlayer insulating films, allowing for efficient interconnection and reduced resistance between power supply lines within and between main lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply lines are arranged in conventional configurations, then wiring resistance increases with distance, but this prevents efficient power distribution across the chip
Solution Approach 1:
The patent transitions from planar power supply line arrangements to a three-dimensional stacked configuration where power supply lines are formed in multiple wiring layers (first, second, and third wiring layers) that extend in the vertical direction. This dimensional change allows power lines to be positioned closer to circuit elements, reducing resistance and improving power distribution efficiency without increasing chip area.
Solution Approach 2:
The patent implements nested power supply lines where a first power supply line and a second power supply line are arranged in parallel within the same wiring layer, and a third power supply line is positioned in an overlapping region in a different wiring layer. This nested arrangement creates multiple parallel conduction paths, effectively reducing overall wiring resistance while maintaining compact spatial utilization.
2Reliability
If power supply lines are extended to cover entire chip areas, then resistance decreases, but chip size increases
Solution Approach 1:
By forming power supply lines in multiple stacked wiring layers rather than extending them horizontally across the entire chip, the patent achieves comprehensive power distribution coverage without proportionally increasing chip area. The vertical stacking allows power lines to serve multiple regions through three-dimensional routing.
Solution Approach 2:
The patent merges multiple power supply functions into overlapping regions where power supply lines from different wiring layers coexist. This consolidation allows a single chip area to support multiple power distribution paths, reducing the total area required compared to conventional extended layouts.
3Loss of energy
If multiple power supply lines are placed in parallel, then resistance is reduced, but circuit placement flexibility is limited
Solution Approach 1:
The patent resolves the conflict between parallel power supply lines and circuit placement flexibility by utilizing vertical separation through multiple wiring layers. Power supply lines in different layers can overlap in the horizontal plane without interfering with circuit element placement, as they are separated by insulating films in the vertical dimension. This allows circuits to be placed in regions between or beneath power lines with greater design freedom.
Data Source
AI summary
A semiconductor device with a power wiring system. The device includes a multi-level wiring structure including a lower-level wiring layer and an upper-level wiring layer over the lower-level wiring layer, and the power wiring system includes a first power supply line and a second power supply line provided as the first-level wiring layer and extending in a first direction in substantially parallel to each other, a third power supply line provided as the upper-level wiring layer and extending in the first direction with overlapping the first power supply line, the first and third power supply lines conveying first and second power voltages, respectively, which are different from each other, and a fourth power supply line provided as the upper-level wiring layer and extending in the first direction with overlapping the second power supply line, the second and fourth power supply lines conveying the second and first power voltages, respectively.