Multi-Level Stack Voltage System for IC Power Efficiency
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Solution Overview
Problem
High-speed electronic systems with integrated circuits face challenges in reducing power consumption and heat generation due to the incompatibility of standard system power supply voltages with low voltage, thin oxide, and small geometry transistor devices, leading to inefficient power usage and noise issues when using linear or switching regulators.
Innovation Solution
A multi-level stack voltage system that partitions the system power supply voltage into smaller supply voltages, allowing low voltage, high speed transistor devices to be used in core circuitry while maintaining compatibility with standard high power supply voltages, achieved through a multi-level stack voltage generator that applies the same current through multiple circuit layers, reducing total current requirements and ensuring appropriate voltage levels for reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard system power supply voltage (3.3V) is used, then compatibility with system applications is maintained, but high-speed transistor devices with thin gate oxide cannot be used
Solution Approach 1:
The patent divides the single standard power supply voltage (e.g., 3.3V) into multiple stacked voltage levels (e.g., V1, V2, V3 where each is approximately 1.1V). This segmentation allows different circuit blocks to operate at appropriate voltage levels for high-speed thin-oxide transistors while maintaining compatibility with the standard system power supply.
2Use of energy by moving object
If linear regulator (LDO) is used to step down power supply voltage, then low power supply voltage is generated for thin oxide transistors, but power efficiency deteriorates due to wasted power drop
Solution Approach 1:
The stacked voltage system allows circuit blocks to serve their own voltage regulation needs by operating at appropriately scaled voltage levels. The total power consumption is reduced because each block operates at the minimum necessary voltage for its function, eliminating the continuous power dissipation inherent in LDOs.
3Loss of energy
If switching regulator is used to generate low power supply, then power efficiency is improved, but device complexity increases due to external inductor requirement
Solution Approach 1:
The patent extracts the voltage scaling function from external power management components (switching regulators with inductors) and implements it directly within the integrated circuit through stacked voltage levels. This eliminates the need for external inductors and associated complexity while maintaining power efficiency.
4Loss of energy
If switching regulator is used to generate low power supply, then power efficiency is improved, but harmful factors increase due to switching noise
Solution Approach 1:
The patent converts the potentially harmful switching noise issue into a benefit by using static stacked voltage levels that eliminate dynamic switching. The voltage levels are established through circuit topology rather than active switching, providing power efficiency without the associated electromagnetic interference that would harm analog circuits.
Data Source
AI summary
An integrated circuit supplied by a rail-to-rail power supply voltage includes a multi-level stack voltage generator configured to partition the rail-to-rail power supply voltage into one or more reduced supply voltages each having a voltage value between positive and negative power supply voltages of the rail-to-rail power supply. The reduced supply voltages and the positive and negative power supply voltages being configured in series to form a stack of circuit layers. The integrated circuit further includes a core circuit including core circuit units coupled in a circuit layer or coupled between two or more circuit layers. Each core circuit unit is coupled to at least one of the reduced supply voltages. The core circuit units are coupled in the stack of circuit layers to form a serial connection of core circuit units between the positive power supply voltage and the negative power supply voltage.