Multi-Level Triggering Circuit Segments Bipolar and CMOS Paths
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Solution Overview
Problem
Digital storage oscilloscopes require high-speed triggering capabilities, which are typically achieved using expensive bipolar logic circuits that consume large amounts of power, and programmable logic does not enable the necessary speeds for advanced triggering features.
Innovation Solution
A multi-level triggering circuit is implemented, segregating high-speed triggering circuitry in an application-specific integrated circuit (IC) and lower-speed, more complex triggering circuitry in a field-programmable gate array (FPGA), allowing for efficient power management and reduced board space by utilizing the FPGA for advanced logic-intensive functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bipolar logic circuits are used for high-speed triggering, then triggering speed is improved, but power consumption increases and cost increases
Solution Approach 1:
The triggering circuit is divided into two separate paths: a first circuit path implemented in bipolar logic for high-speed triggering, and a second circuit path implemented in CMOS logic for lower-speed advanced triggering. This segmentation allows each path to operate at its optimal speed while consuming appropriate power levels, resolving the contradiction between high triggering speed and low power consumption.
2Speed
If bipolar logic circuits are used for high-speed triggering, then triggering speed is improved, but device cost increases
Solution Approach 1:
The triggering functionality is segmented into two paths with different implementation technologies. The first path uses expensive bipolar logic only where high speed is absolutely necessary, while the second path uses cheaper CMOS logic for advanced triggering features. This selective segmentation reduces overall device cost while maintaining high-speed capability where required.
3Device complexity
If programmable logic is used for triggering, then device complexity is reduced and cost is lowered, but triggering speed is insufficient
Solution Approach 1:
The circuit is segmented such that simple high-speed triggering functions are implemented in bipolar logic for maximum speed, while complex advanced triggering functions are implemented in CMOS programmable logic. This segmentation allows programmable logic to handle complexity without sacrificing the speed required for basic triggering operations.
4Speed
If a single high-speed circuit path is used, then triggering speed is maximized, but advanced triggering features cannot be implemented
Solution Approach 1:
The triggering system is segmented into two parallel paths: the first path provides high-speed triggering with simple edge detection, while the second path provides lower-speed advanced triggering with complex pattern recognition and processing capabilities. This segmentation enables the system to support both high-speed basic triggering and versatile advanced triggering features simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces power consumption and board space while enabling high-speed triggering and advanced triggering features, making it suitable for digital storage oscilloscopes and other instruments that require precise triggering.
Implementation Method 1
a comparator to compare an input analog signal to a threshold and to output a signal that is based on the comparison
Data Source
AI summary
Circuitry includes a comparator to compare an input analog signal to a threshold and to output a signal that is based on the comparison; a first circuit path to receive the signal and to detect a characteristic of the signal, where the first circuit path is configured to support triggering at a first frequency; a second circuit path to receive the signal and to detect the characteristic of the signal, where the second circuit path is configured to support triggering at a second frequency that is lower than the first frequency; and a selector to select an output of the first circuit path or an output of the second circuit path.