Multi-Level Word Line Routing for SRAM Resistance Reduction
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Solution Overview
Problem
The increasing resistance of conductive lines in semiconductor integrated circuits limits the operating frequency of digital signals, particularly in SRAM circuits, due to the smaller geometry sizes and higher unit-length resistance, which affects the performance and efficiency of memory circuits.
Innovation Solution
A word line and bit line routing scheme that splits word lines across multiple levels of the memory circuit, effectively widening them while maintaining compliance with design rules, reduces word line resistance and improves operating frequency by optimizing the layout and arrangement of conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then the number of interconnected devices per chip area increases, but the unit-length resistance of conductive lines becomes greater
Solution Approach 1:
The patent implements a multi-level word line structure where conductive lines are routed across different vertical levels (first level and second level) connected by vias. This three-dimensional routing approach allows word lines to maintain adequate width and lower resistance while accommodating higher functional density, effectively resolving the contradiction between miniaturization and signal transmission quality.
2Productivity
If the width of conductive line is decreased to increase functional density, then more devices can be packed per chip area, but the operating frequency of digital signals is limited
Solution Approach 1:
By routing word lines across multiple vertical levels, the patent maintains adequate line width for low resistance while increasing functional density. The multi-level structure allows signals to traverse shorter horizontal distances at each level, effectively maintaining operating frequency despite increased device packing density.
Solution Approach 2:
The word line is segmented into multiple portions routed at different levels (first word line portion at first level, second word line portion at second level). This segmentation allows each segment to be optimized for signal transmission while the overall structure achieves higher functional density.
3Productivity
If unit-length resistance of conductive line is increased due to smaller geometry, then functional density improves, but the rising or falling time of digital signal becomes longer
Solution Approach 1:
The multi-level routing structure reduces the effective path length and maintains adequate conductor width, thereby keeping resistance low despite smaller geometry sizes. This enables faster signal transitions (shorter rising/falling times) while achieving higher functional density.
Data Source
AI summary
A method of designing a memory circuit is provided that includes generating a layout of a first memory cell using an integrated circuit design system. The layout of the first memory cell is generated by routing a first word line in a first layer on a first level, and routing a second word line in the first layer. Also, the method includes generating a layout of a second memory cell using the integrated circuit design system. The layout of the second memory cell is generated by routing a third word line in the first layer, the second word line being between the first word line and the third word line, and routing a fourth word line in the first layer, the third word line being between the second word line and the fourth word line. Moreover, the method includes assigning a first color scheme to the first word line and to the third word line, and assigning a second color scheme to the second word line and to the fourth word line. The first color scheme is associated with a first manufacturing process using a first mask and the second color scheme is associated with a second manufacturing process using a second mask.