Multi-Line Gate Drive Shift Register for Narrow-Bezel Displays
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Solution Overview
Problem
Existing display technologies face challenges in achieving high integration and low cost, particularly in the integration of thin film transistor (TFT) gate drive circuits on array substrates, where the drive control circuits are inefficient and require multiple shift register units, leading to increased complexity and bezel width.
Innovation Solution
A shift register unit design incorporating first and second control circuits, cascade output circuits, and drive output circuits, which allow for the selection and output of signals from multiple drive nodes to cascade and drive output ends, enabling a single shift register unit to drive multiple gate lines, thereby reducing the number of units needed and allowing for narrow bezel designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple shift register units are used to drive gate lines, then the drive control capability is improved, but the device complexity and bezel width increase
Solution Approach 1:
The patent implements multi-functionality by enabling a single shift register unit to drive multiple gate lines through multiple output circuits (first output circuit, second output circuit, third output circuit) that can be selectively activated. The control circuit receives selection signals to determine which output circuit is active, allowing one unit to perform the function of multiple units while reducing overall device complexity and bezel width
2Adaptability or versatility
If multiple shift register units are used to drive gate lines, then the drive control capability is improved, but the integration density decreases
Solution Approach 1:
The patent merges multiple drive functions into a single shift register unit by integrating multiple output circuits (first, second, and third output circuits) within one unit. These output circuits can be selectively activated through control logic, combining the capabilities of what would traditionally require separate units. This merging approach increases integration density by reducing the total area occupied while maintaining comprehensive drive control capability
Data Source
AI summary
A shift register unit, a gate drive circuit, a display apparatus and a driving method. The shift register unit includes: a first control circuit, configured to control a signal of a first node and a signal of a second node according to a signal of an input signal end and a signal of a first clock signal end; second control circuits, configured to control signals of at least two drive nodes according to the signal of the first node, the signal of the second node and signals of second clock signal ends; cascade output circuits, configured to provide the signal of one of the at least two drive nodes to a cascade output end according to cascade selection signal ends; and drive output circuits, configured to provide the signal of at least one of the at least two drive nodes to drive output ends corresponding to the drive nodes.