Multi-Liner STI Structure for Etch-Induced Short Prevention

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Solution Overview

Problem

The complexity of manufacturing and integration in semiconductor devices leads to deficiencies, necessitating an improved manufacturing process to address these issues.

Innovation Solution

A semiconductor device structure and method involving multiple liners in shallow trench isolation (STI) structures, where different materials are used for the liners to prevent electrical shorts during etching processes, enhancing device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple liners are used in STI structures, then reliability is improved by preventing electrical shorts, but device complexity increases due to additional manufacturing steps

Engineering Contradiction:
Improveelectrical short preventionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure is divided into multiple functional liners (first liner, second liner, third liner) with different materials and purposes. The first liner contacts the well region for selective etching protection, the second liner covers the first liner for additional isolation, and the third liner covers the second liner for final protection. This segmentation allows each layer to address specific reliability concerns while maintaining overall device performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multiple liners act as intermediary protective layers between the etching process and the semiconductor substrate. Each liner material is selected to provide different etching selectivities, creating a graduated protection system that mediates the interaction between aggressive etching chemistry and sensitive device structures, preventing electrical shorts without requiring excessive process complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If different materials are used for liners, then etching selectivity is improved for precise sidewall protection, but manufacturing precision requirements increase

Engineering Contradiction:
Improveetching selectivityVSAvoidliner deposition precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

Different liner materials are assigned to different locations and functions within the STI structure. The first liner (contacting well region) uses material with high etching selectivity for sidewall protection, the second liner uses material optimized for coverage and adhesion, and the third liner uses material providing final protection and planarity. This local quality assignment allows each layer to be optimized for its specific function while maintaining overall manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The STI structure employs a composite multi-layer liner system where each layer is made of different materials selected for specific properties. This composite approach combines the advantages of different materials (etching selectivity, adhesion, protection) in a single integrated structure, achieving superior overall performance while managing manufacturing precision through established deposition techniques for each material type.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS11842921B2Method for preparing semiconductor device structure with multiple liners
Publication Date: 2023.12.12 NAN YA TECH
  • US11842921B2 patent drawing
  • US11842921B2 patent drawing
  • US11842921B2 patent drawing

AI summary

The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a pad oxide layer over a semiconductor substrate; forming a pad nitride layer over the pad oxide layer; forming a shallow trench penetrating through the pad nitride layer and the pad oxide layer and extending into the semiconductor substrate; forming a first liner, a second liner and a third liner over sidewalls and a bottom surface of the semiconductor substrate in the shallow trench; filling a remaining portion of the shallow trench with a trench filling layer over the third liner; and planarizing the second liner, the third liner and the trench filling layer to expose the pad nitride layer. The first liner and the remaining portions of the second liner, the third liner and the trench filling layer collectively form a shallow trench isolation (STI) structure in an array area.