Multi-Load FIFO Buffer for Single-Cycle Request Handling
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Solution Overview
Problem
FIFO data buffers in computing devices face inefficiencies when handling multiple input-output requests in a single clock cycle, leading to increased circuit size and power consumption, particularly in mobile devices with limited power sources.
Innovation Solution
A FIFO data buffer system comprising a load shift register, request line encoder, and state machine that prioritizes and sorts incoming requests based on priority values, allowing multiple requests to be loaded and managed efficiently within a smaller circuit footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a FIFO data buffer handles multiple input-output requests in a single clock cycle, then data flow efficiency is improved, but circuit size and power consumption increase
Solution Approach 1:
The FIFO data buffer is divided into multiple independent banks (first bank, second bank, third bank, fourth bank), each capable of handling requests independently. This segmentation allows parallel processing of multiple requests across different banks within the same clock cycle, improving data flow efficiency without requiring a single large circuit structure that would consume excessive area and power.
2Productivity
If a FIFO data buffer handles multiple input-output requests in a single clock cycle, then data flow efficiency is improved, but power consumption increases
Solution Approach 1:
By segmenting the FIFO into multiple smaller banks, each bank can be independently controlled and powered. This allows the system to activate only the necessary banks for current operations, reducing overall power consumption compared to a single large FIFO that would require all components to be active simultaneously to handle multiple requests.
Solution Approach 2:
The system dynamically selects which bank to use based on current request patterns and data flow requirements. The dynamic bank selection mechanism enables the FIFO to adapt its active components to actual workload demands, improving data flow efficiency while minimizing power consumption by keeping unnecessary banks in low-power states.
3Adaptability or versatility
If multiple requests are loaded into the load shift register, then request handling capability is improved, but device complexity increases
Solution Approach 1:
The load shift register is divided into multiple independent load shift registers (first, second, third, fourth), each associated with a specific bank. This segmentation allows the system to load multiple requests in parallel across different registers, improving request handling capability while keeping each individual register relatively simple in structure, thereby managing device complexity.
Data Source
AI summary
One example provides a device comprising a FIFO data buffer comprising a load shift register, a request line encoder, a state machine, and one or more clocks to provide a clock signal. The load shift register comprises a plurality of register locations and is configured to shift data between at least two register locations controllable on at least one shift instruction and to load data into at least one of the register locations controllable on at least one load instruction. The request line encoder is configured to receive one or more requests each comprising a corresponding priority value, and to determine a request number value representing a number of requests to load into the load shift register. The state machine is configured to determine, based at least in part on the request number value, a state, one or more shift instructions, and one or more load instructions.