Multi-Load FIFO Buffer for Priority Sorting in One Clock Cycle
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Solution Overview
Problem
FIFO data buffers in computing devices face inefficiencies when handling multiple input-output requests within a single clock cycle, leading to increased circuit size and power consumption, particularly in mobile devices with limited power resources.
Innovation Solution
A FIFO data buffer system incorporating a load shift register, request line encoder, and state machine to manage and prioritize multiple requests based on priority values, allowing efficient loading and sorting of requests within a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a FIFO data buffer handles multiple input-output requests within a single clock cycle, then data flow efficiency is improved, but circuit size and power consumption increase
Solution Approach 1:
The buffer is divided into multiple banks (first bank, second bank, third bank, fourth bank) that can be independently controlled. Each bank has its own load and shift operations, allowing parallel processing of multiple requests while maintaining efficient data flow without proportionally increasing power consumption across the entire buffer.
Solution Approach 2:
The patent implements dynamic control of load and shift operations based on priority values and request timing. The buffer can adaptively enable or disable loading and shifting in different banks within the same clock cycle, allowing efficient handling of multiple requests while minimizing unnecessary power consumption in inactive regions.
2Productivity
If a FIFO data buffer handles multiple input-output requests within a single clock cycle, then data flow efficiency is improved, but circuit gate count increases
Solution Approach 1:
The buffer is divided into multiple banks (first bank, second bank, third bank, fourth bank) that can be independently controlled. Each bank has its own load and shift operations, allowing parallel processing of multiple requests while maintaining efficient data flow without proportionally increasing power consumption across the entire buffer.
Solution Approach 2:
The buffer structure uses universal control mechanisms that can handle multiple requests with different priorities through the same basic load and shift infrastructure. The priority-based control logic provides a universal solution for managing multiple requests without requiring separate dedicated circuits for each request, reducing overall gate count.
3Productivity
If requests are prioritized and sorted within a single clock cycle, then request handling efficiency is improved, but control logic complexity increases
Solution Approach 1:
Requests are assigned priority values in advance before being loaded into the buffer. This preliminary assignment of priority values allows the buffer to efficiently manage multiple requests without requiring complex real-time sorting logic, as the prioritization decision is made beforehand based on request characteristics.
Solution Approach 2:
The buffer implements dynamic control of load and shift operations based on priority values and request timing. The buffer can adaptively enable or disable loading and shifting in different banks within the same clock cycle, allowing efficient handling of multiple requests while minimizing unnecessary power consumption in inactive regions.
Data Source
AI summary
One example provides a device comprising a FIFO data buffer comprising a load shift register, a request line encoder, a state machine, and one or more clocks to provide a clock signal. The load shift register comprises a plurality of register locations and is configured to shift data between at least two register locations controllable on at least one shift instruction and to load data into at least one of the register locations controllable on at least one load instruction. The request line encoder is configured to receive one or more requests each comprising a corresponding priority value, and to determine a request number value representing a number of requests to load into the load shift register. The state machine is configured to determine, based at least in part on the request number value, a state, one or more shift instructions, and one or more load instructions.