Multi-Locking Frequency Synthesizer for Faster Clock Hopping
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Solution Overview
Problem
Existing frequency synthesizers face limitations in locking speed and power consumption, particularly in high-speed systems, due to the frequency of the reference clock signal, which restricts their application in high-speed hopping systems and increases system loading.
Innovation Solution
A frequency synthesizer design that includes multiple frequency locking circuits, a selecting circuit, and a control circuit to manage and control these circuits, allowing for flexible operation with fewer circuits and reduced power consumption by selectively locking clock signals to reference clock signals, thereby enhancing settling time and reducing unnecessary power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a single frequency locking circuit is used to lock clock signals sequentially, then power consumption is reduced, but the settling time is extended and system speed is limited
Solution Approach 1:
The system divides the frequency locking function into multiple parallel locking circuits (first locking circuit, second locking circuit, etc.), each capable of independently locking different clock signals. This segmentation allows simultaneous locking operations, reducing total settling time while maintaining power efficiency through selective activation of circuits based on hopping patterns.
Solution Approach 2:
The control circuit pre-locks non-output clock signals to their corresponding reference clock signals before they are needed for frequency hopping. This preliminary locking action ensures that when a frequency hop is required, the target clock signal is already locked and ready, eliminating delays and reducing overall settling time.
2Loss of time
If the reference clock signal frequency is increased to improve locking speed, then settling time is reduced, but power consumption and system loading increase
Solution Approach 1:
The system dynamically configures the locking state of multiple frequency locking circuits based on the current frequency hopping requirements. The control circuit activates only the necessary locking circuits at any given time, allowing faster locking when needed while minimizing power consumption during stable operation. This dynamic adaptation resolves the contradiction between speed and power efficiency.
3Speed
If multiple frequency locking circuits operate simultaneously to reduce settling time, then locking speed improves, but power consumption and circuit area increase
Solution Approach 1:
Each frequency locking circuit is designed to be multi-functional, capable of locking any clock signal to its corresponding reference clock signal. The control circuit intelligently assigns clock signals to available locking circuits based on current system needs, allowing the same hardware resources to serve multiple purposes. This universality enables fast parallel locking when needed while allowing circuits to remain inactive or share resources during lower-demand periods, reducing overall power consumption.
Data Source
AI summary
The present invention discloses a frequency synthesizer, including: a plurality of frequency locking circuits, for locking a plurality of clock signals to output the clock signals according to a plurality of reference clock signals respectively; a selecting circuit, for selecting a specific clock signal from the clock signals as an output clock signal, wherein a specific frequency locking circuit of the frequency locking circuits locks the specific clock signal; and a control circuit, for controlling the frequency locking circuits. The control circuit controls at least one of the frequency locking circuits apart from the specific frequency locking circuit to lock another clock signal according to another reference clock signal at the same time. A related method for frequency synthesizing is also disclosed.