Multi-Loop PLL Clock Generation for Low-Jitter Fractional Division
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Solution Overview
Problem
Conventional fractional frequency dividers introduce jitter and quantization noise into high-speed clock signals, requiring complex phase error correction and large phase range support, which increases costs and reduces bandwidth efficiency in phase-locked loops.
Innovation Solution
A multi-loop clock signal generator using multiple phase-locked loops and a target frequency calculation circuit to adjust divider values independently of the voltage-controlled oscillator's output, allowing for low-jitter clock generation by measuring frequency offsets relative to a stable reference signal during loop settling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional fractional frequency dividers are used to generate reference and feedback clock signals, then the clock signal frequency can be divided to target frequencies, but jitter and quantization noise are introduced into the clock signals
Solution Approach 1:
The patent divides the frequency division function into two separate loops: an inner loop that generates a stable intermediate clock signal with minimal jitter, and an outer loop that performs the final frequency division to achieve target frequencies. This segmentation allows each loop to be optimized independently, with the inner loop focusing on stability and the outer loop on frequency accuracy.
Solution Approach 2:
The patent introduces an intermediate clock signal as a mediator between the reference clock and the final output. This intermediate signal serves as a stable foundation that reduces the burden on the fractional frequency divider, thereby minimizing jitter and quantization noise in the final output while still achieving the required frequency division.
2Reliability
If conventional phase error correction techniques are used to address jitter, then jitter can be reduced, but the techniques are complex, introduce spurs, and increase costs
Solution Approach 1:
The patent applies preliminary action by ensuring that the inner loop establishes a stable, low-jitter intermediate clock signal before the outer loop begins frequency division. This preliminary stabilization reduces the need for complex phase error correction in the outer loop, as the input to the fractional divider already has minimal jitter.
Solution Approach 2:
The patent extracts the jitter-sensitive frequency division function from the phase-critical reference signal generation and places it in a separate outer loop that operates on already-stabilized signals. This extraction allows the inner loop to focus solely on stability while the outer loop handles frequency accuracy with minimal phase error correction requirements.
3Speed
If conventional fractional frequency dividers are used, then frequency division can be achieved, but the phase-locked loop must have a low bandwidth to filter quantization noise
Solution Approach 1:
The patent segments the frequency division process into two stages: the inner loop performs coarse frequency division with high bandwidth for fast settling, while the outer loop performs fine frequency division with lower bandwidth for noise filtering. This segmentation allows each loop to operate at optimal bandwidth without compromising overall system performance.
Solution Approach 2:
The patent applies local quality by assigning different bandwidth characteristics to different parts of the frequency division process. The inner loop uses high bandwidth near the reference frequency for fast acquisition, while the outer loop uses lower bandwidth near the output frequency for noise filtering, optimizing both speed and noise performance in their respective frequency ranges.
4Speed
If conventional fractional frequency dividers are used to generate reference and feedback clock signals, then the clock signals can be generated at target frequencies, but the phase frequency detector must support a large full-scale phase range
Solution Approach 1:
The patent applies preliminary action by pre-stabilizing the phase relationship in the inner loop before the signal enters the outer loop. This preliminary phase stabilization reduces the phase range variations that the phase frequency detector in the outer loop must handle, allowing it to operate with a smaller, more manageable phase range while still achieving accurate target frequency generation.
Data Source
AI summary
A multi-loop clock signal generator includes a first phase-locked loop circuit configured to generate a control signal and a voltage-controlled oscillator configured to generate an output clock signal based on the control signal. The clock signal generator includes a second phase-locked loop circuit configured to generate an adjusted first divider value for the first phase-locked loop circuit. The clock signal generator further includes a target frequency calculation circuit configured to calculate a target frequency for the second phase-locked loop circuit based on a target frequency ratio of the second phase-locked loop circuit calculated based on frequency offset ratios of the first and second clock signals with respect to a reference signal.