Multi-Loop Ring Oscillator for Orthogonal Low-Jitter Signals
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Solution Overview
Problem
Existing ring VCOs face challenges in achieving low jitter and phase noise performance, particularly due to high sensitivity to power supply voltage variations and inability to generate orthogonal signals with even numbers of inverter stages, which affects their frequency variable range and symmetry.
Innovation Solution
An oscillating circuit design featuring a main loop circuit with even numbers of inverting circuits cascaded in a ring, supplemented by auxiliary loop circuits connected in parallel, which maintains symmetry and reduces voltage oscillation at the tail node, thereby enhancing phase difference accuracy and reducing sensitivity to power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a ring VCO uses an odd number of inverter stages, then oscillation can be achieved, but orthogonal signal generation is impossible
Solution Approach 1:
The ring VCO is divided into a main loop circuit with N inverters (N is even) and multiple auxiliary loop circuits, each with an odd number of inverters. The main loop provides the even-stage oscillation framework, while auxiliary loops enable orthogonal signal generation by creating additional oscillation paths with appropriate phase shifts.
Solution Approach 2:
The patent transitions from a single-loop oscillation structure to a multi-loop structure by adding auxiliary loop circuits. This dimensional expansion allows the system to generate multiple oscillation modes including orthogonal signals, overcoming the limitation of single-loop even-stage inverters.
2Adaptability or versatility
If a ring VCO uses an even number of inverter stages, then orthogonal signal generation becomes possible, but the circuit enters a stable latch state and cannot oscillate
Solution Approach 1:
The even-stage inverter ring is segmented into a main loop (even stages) and auxiliary loops (odd stages). The auxiliary loops break the stable latch state of the main loop by introducing additional feedback paths that enable oscillation while preserving the orthogonal signal generation capability provided by the even-stage structure.
Solution Approach 2:
The auxiliary loop circuits act as intermediaries that mediate between the even-stage main loop and the oscillation requirement. They provide the necessary disturbance to prevent latch state stability while maintaining the overall even-stage architecture needed for orthogonal signal generation.
3Adaptability or versatility
If variable loads are provided on both power supply and ground sides of CMOS structure, then frequency control is achieved, but circuit asymmetry increases sensitivity to power supply voltage
Solution Approach 1:
Variable loads are selectively provided only on the ground side of the CMOS structure, not on both power supply and ground sides. This localized approach maintains frequency control capability through ground-side load modulation while avoiding the circuit asymmetry that would increase sensitivity to power supply voltage variations.
Solution Approach 2:
The patent intentionally creates a controlled asymmetry by placing variable loads only on the ground side rather than symmetrically on both power supply and ground sides. This asymmetric configuration achieves frequency control while actually reducing power supply sensitivity compared to fully symmetric designs.
4Reliability
If inductors are used in LCVCO to achieve low jitter performance, then jitter performance improves, but circuit area increases and electromagnetic interference occurs
Solution Approach 1:
The patent replaces the mechanical/physical inductor component with an all-transistor ring VCO structure. This substitution eliminates the need for large-area inductors while achieving low jitter performance through optimized transistor-based delay elements and symmetric circuit design, thereby reducing both area and electromagnetic interference.
Data Source
AI summary
An oscillating circuit includes N nodes outputting oscillating signals, a main loop circuit including N inverting circuits, and a plurality of auxiliary loop circuits. Each inverting circuit in the auxiliary loop circuits is connected in parallel with even numbers of inverting circuits cascaded in the main loop circuit. The circuits for feeding back signals from outputs to inputs of the respective inverters of the main loop circuit have circuit configurations equivalent to each other. Each inverting circuit in the main loop circuit and the auxiliary loop circuits drives an output line such that a phase of an output signal is inverted with respect to a phase of an input signal and has driving power that becomes lower when the phases of the output signal and the input signal are inverted with respect to each other than when the output signal and the input signal are in phase with each other.