Multi-Mask Patterning for Tightly Spaced IC Interconnects
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Solution Overview
Problem
Traditional photolithography methods struggle to pattern interconnect lines that are closely spaced, resulting in a lack of contrast between exposed and unexposed photoresist regions, making it difficult to form interconnect lines in extremely close proximity.
Innovation Solution
The use of multiple photolithography masks, where one mask includes a series of longitudinal segments and coupling segments that traverse to connect with segments on another mask, allowing for more precise patterning of tightly spaced features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional single-mask photolithography is used, then the manufacturing process is simple, but it becomes impossible to pattern interconnect lines in extremely close proximity due to lack of contrast between exposed and unexposed photoresist regions
Solution Approach 1:
The patent divides a single IC layer into multiple subsets, with each subset assigned to a separate photolithography mask. This segmentation allows each mask to pattern a specific subset of features with adequate spacing, avoiding the contrast problems that arise when all features are attempted on a single mask. The layer is partitioned into first and second subsets, each processed by dedicated masks.
Solution Approach 2:
The patent introduces a new dimension of complexity by using multiple masks for a single layer, moving from the traditional one-mask-per-layer approach. This dimensional change in the manufacturing process enables precise patterning of closely spaced interconnect lines by distributing features across multiple masks, each handling a subset of the total features.
2Productivity
If feature sizes are shrunk to pack more transistors, then integrated circuits exhibit improved speed and power characteristics, but it becomes difficult to continue shrinking from one technology node to the next
Solution Approach 1:
By segmenting the IC layer into multiple subsets and assigning each to a separate mask, the patent enables continued feature size shrinkage. Each mask handles a reduced subset of features, maintaining adequate spacing and contrast even as individual features become smaller. This allows transistor density to increase while preserving manufacturability.
Solution Approach 2:
The patent changes the parameter of mask assignment from one mask per layer to multiple masks per layer. This parameter change enables continued scaling by allowing each mask to be optimized for its specific subset of features, maintaining the necessary contrast and spacing relationships even as overall feature dimensions shrink.
3Manufacturing precision
If multiple photolithography masks are generated for a single IC layer, then features can be patterned in extremely close proximity with improved resolution, but the photolithography mask set becomes more complex
Solution Approach 1:
The patent segments the IC layer features into multiple subsets, with each subset assigned to a separate mask. This segmentation achieves high resolution for closely spaced features by ensuring adequate spacing within each subset, while the number of masks is optimized to balance resolution requirements with manufacturing complexity.
Solution Approach 2:
The patent applies local quality by assigning different subsets of features to different masks based on their spatial relationships and spacing requirements. Each mask is optimized for its specific subset, allowing high-resolution patterning where needed while avoiding unnecessary complexity in other regions. The coupling segments are strategically placed to connect features across mask boundaries.
Data Source
AI summary
One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first series has fewer than all of the longitudinal segments in the IC layer. A second electronic mask is also generated for the IC layer. The second electronic mask includes a second series of longitudinal segments from the IC layer, where the second series has fewer than all of the longitudinal segments in the IC layer and differs from the first series. The first and second masks are generated so a coupling segment extends traverse to the first direction and couples one longitudinal segment on the IC layer to another longitudinal segment on the IC layer.