Multi-Master Bus Arbitration Protocol for Uninterrupted Transactions
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Solution Overview
Problem
The Inter-Integrated Circuit (I2C) bus protocol limits the control a bus master can assert over the bus, restricting reliable transactions and is unsuitable for applications requiring uninterrupted multi-transaction sequences, leading to potential data inconsistency issues.
Innovation Solution
The introduction of additional I/O lines and a modified arbitration protocol allows a master to perform multiple consecutive transactions on the I2C bus while preventing other masters from intervening, ensuring exclusive access to a slave device for uninterrupted sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the I2C bus protocol allows multiple masters to access the bus, then bus utilization and system flexibility are improved, but data consistency and transaction reliability deteriorate due to potential interruptions
Solution Approach 1:
The patent introduces a bus arbitrator as an intermediary component that mediates between multiple masters and the slave device. The arbitrator receives arbitration signals from masters, determines which master should have bus access, and controls the bus accordingly. This intermediary mechanism allows multiple masters to share the bus (improving utilization) while ensuring that only one master accesses the bus at a time during critical transactions (maintaining data consistency).
Solution Approach 2:
The patent implements a feedback mechanism where masters send arbitration signals to indicate their intent to access the bus, and the bus arbitrator responds by granting or denying bus access. This feedback loop allows the system to dynamically manage bus access based on current transaction needs, enabling reliable multi-master operation by continuously monitoring and responding to master requests.
2Device complexity
If the I2C protocol restricts masters to single transactions, then bus arbitration simplicity is improved, but transaction completeness and operational efficiency worsen for sequences requiring multiple uninterrupted transactions
Solution Approach 1:
The patent applies preliminary action by requiring masters to signal their arbitration intent before actually accessing the bus. The bus arbitrator processes these preliminary signals and determines bus access rights in advance. This allows the system to maintain simple arbitration rules while enabling masters to perform sequences of transactions without interruption, as the arbitrator grants continuous access based on the initial arbitration decision.
Solution Approach 2:
The patent introduces dynamic bus access control where the bus arbitrator can grant extended access to a master for multiple consecutive transactions based on the initial arbitration outcome. This dynamic mechanism allows the system to adapt to different transaction scenarios - simple single transactions or complex multi-transaction sequences - while maintaining a relatively simple arbitration protocol structure. The arbitrator dynamically adjusts bus access duration based on transaction requirements.
Data Source
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AI summary
Embodiments of the invention provide systems, methods, and apparatus for arbitrating a multi-master computer bus. The embodiments include a multi-master serial computer bus; a first master coupled to the bus; a second master coupled to the bus; a slave device coupled to the bus; a first I/O line from the first master going to the second master and the slave device; and a second I/O line from the second master going to the first master and the slave device. A bus arbitration protocol for arbitrating use of the bus restricts the masters to a single transaction each time either master becomes a bus master, and the masters are each adapted to use the I/O lines to signal to each other not to become a bus master. Numerous other aspects are disclosed.