Multi-Master GPIO Control Circuit for Stable Processor Arbitration
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Solution Overview
Problem
Conventional methods for controlling multiple master control terminals in a multi-master GPIO mode on a server or computer motherboard result in system failures or damage when one processing end fails to release a preset voltage level, preventing the other processing end from accessing hardware due to electrical connections.
Innovation Solution
A multi-master control circuit incorporating a signal switch, D-type flip-flop, and multiplexer to manage control signals from multiple processors, ensuring that only one processor with higher authority can access hardware at a time, using feedback and selection signals to coordinate access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two master control terminals are electrically connected to control GPIO pins of a switch, then both terminals can control the switch via the GPIO pins, but when one terminal switches the SPD busbar to be electrically connected to itself and does not release the preset voltage level, the other terminal cannot perform access, resulting in system failure
Solution Approach 1:
The patent introduces an intermediary control circuit between the two master control terminals that includes a signal switch, D-type flip-flop, and multiplexer. This intermediary circuit mediates the control signals from both terminals, ensuring that only one terminal can access the SPD busbar at a time through coordinated switching, while the other terminal is blocked from accessing. The intermediary circuit prevents direct conflict between the two terminals by managing their access requests through a structured control mechanism.
Solution Approach 2:
The patent implements a feedback mechanism where the control circuit monitors the state of control signals from both master terminals and adjusts the switching accordingly. The D-type flip-flop captures the state of control signals and provides feedback to the signal switch and multiplexer, ensuring that the system maintains a stable state where only one terminal has access at a time. This feedback loop prevents the scenario where both terminals simultaneously hold the busbar, thereby avoiding system failure.
2Ease of operation
If switching control pins are electrically connected to jointly control the switch, then both processors can access the SPD system busbar, but control authority becomes unstable and conflicts arise when one processor does not release the busbar
Solution Approach 1:
The patent employs dynamic control where the signal switch and multiplexer can change their connection states based on the control signals received from the master terminals. The D-type flip-flop dynamically captures and stores the state of control signals, enabling the system to adaptively switch between different access configurations. This dynamic behavior ensures that control authority is stable and predictable, as the system transitions between states in a controlled manner rather than allowing arbitrary simultaneous access.
Solution Approach 2:
The patent segments the control function into distinct components: the signal switch handles the initial control signal routing, the D-type flip-flop manages state storage and timing, and the multiplexer handles the final access routing to the SPD busbar. This segmentation of control functions allows each component to perform its specific task reliably, ensuring that control authority is properly managed and conflicts are prevented through structured functional division.
Data Source
AI summary
A multi-master control circuit includes signal switch, D-type flip-flop, and multiplexer. The signal switch outputs switching signals based on a first control signal generated by a first processor or a second control signal generated by a second processor. The D-type flip-flop includes clock input, signal input, signal output, and inverted signal output. The clock input is coupled to the signal switch to receive the switching signals, and the inverted signal output is coupled to the signal input. Upon triggering by the switching signals, the signal output of the D-type flip-flop generates a selection signal. The multiplexer receives a first access signal generated by the first processor and a second access signal generated by the second processor. The multiplexer is coupled to the signal output of the D-type flip-flop to receive the selection signal and output either the first access signal or the second access signal based on the selection signal.