Multi-Master SPI Interconnect Circuit Arbitration
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Solution Overview
Problem
Conventional serial peripheral interface (SPI) buses are limited in supporting multiple master devices, leading to collisions and inefficiencies in complex device configurations, particularly in mobile communication devices with increased functionality.
Innovation Solution
The implementation of a multi-master SPI bus system that allows two or more master devices to initiate transactions without causing collisions by using an interconnect circuit with an arbiter and switch to manage point-to-point connections, buffer data and chip select information, and prevent conflicts between master devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SPI bus protocols are used to support multiple master devices, then device functionality and complexity increase, but collisions occur between master devices
Solution Approach 1:
An interconnect circuit is introduced as an intermediary between multiple master devices and the SPI bus. This interconnect circuit includes arbitration logic that receives transactions from multiple masters, determines which master should proceed based on arbitration rules, and grants permission to the selected master. This mediator prevents direct collisions by controlling access to the shared SPI bus resources.
Solution Approach 2:
The system dynamically switches between different operational modes: single-master mode for simple configurations and multi-master mode with arbitration for complex configurations. The interconnect circuit can dynamically grant or deny access to the SPI bus based on current transaction states, arbitration outcomes, and bus availability, allowing flexible adaptation to different operational scenarios.
2Device complexity
If a single SPI bus is shared among multiple master devices, then device complexity is reduced, but transaction collisions and conflicts increase
Solution Approach 1:
The system segments the SPI bus operations into separate point-to-point transactions. Each master device communicates with slave devices through dedicated point-to-point links that are selectively activated. The interconnect circuit divides the shared bus into multiple virtual channels, allowing simultaneous point-to-point transactions between different master-slave pairs without interference.
Solution Approach 2:
The interconnect circuit performs preliminary arbitration before granting bus access. Masters must register their transactions with the interconnect circuit in advance, which then determines the transaction order and grants permission before data transfer begins. This preliminary scheduling prevents collisions by ensuring only authorized masters access the bus at any given time.
3Reliability
If point-to-point SPI links are used for each master device, then collision-free communication is achieved, but device interconnection complexity increases
Solution Approach 1:
The interconnect circuit performs multiple functions within a single integrated structure: it acts as an arbiter for transaction scheduling, a switch for point-to-point connection establishment, and a controller for bus access management. This universal component handles all interconnection needs for multiple masters and slaves, reducing the need for separate complex interconnection structures.
Solution Approach 2:
The system merges the arbitration logic, switching fabric, and bus control functions into a single interconnect circuit. Instead of having separate arbitration units, switching matrices, and control logic for each master device, these functions are combined in one centralized interconnect that manages all point-to-point transactions efficiently.
Data Source
AI summary
Systems, methods, and apparatus provide a multi-master serial peripheral interface. An apparatus is coupled to master and slave devices through an interconnect circuit using individual point-to-point SPI links. The interconnect circuit may be configured to couple pairs of devices selected from the plurality of devices through their individual point-to-point SPI links, enable a first transaction to be completed between a first pair of devices after a first master device in the first pair of devices initiates the first transaction, enable a second transaction to be completed between a second pair of devices after a second master device in the second pair of devices initiates the second transaction, and prevent a collision between the first master device and the second master device while the first pair of devices are engaged in the first transaction. The pairs of devices may be selected when they are participants in one or more transactions.