Multi-Memory Array Access via Shared MIO Lines
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Solution Overview
Problem
In dynamic random-access memory (DRAM), the increased length of signal lines due to re-orienting arrays to fit more memory in a smaller area leads to higher resistance and longer access times, complicating the layout and increasing the die size, which can exceed desired maximum operation times during fast memory access cycles.
Innovation Solution
Implementing dual memory arrays with dual access blocks that share main input/output (MIO) lines to reduce the number of signal lines needed, using line select repeaters to improve signal integrity and enable faster column-to-column decode operations, and employing NAND logic in write drivers and read sense amplifiers to manage data transmission efficiently across memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If arrays are re-oriented to fit more memory in a smaller area, then memory density increases, but signal line length increases leading to higher resistance and longer access times
Solution Approach 1:
The patent introduces a vertical dimension by routing signal lines through layers above or below the memory arrays using interconnect structures. This allows signal lines to bypass the horizontal plane occupied by memory arrays, effectively reducing the physical path length and resistance while maintaining high memory density through vertical stacking of interconnect layers.
Solution Approach 2:
The patent introduces intermediate buffer circuits and signal repeaters positioned at strategic locations within the memory array. These intermediaries refresh and amplify signals during transmission, compensating for the increased resistance and signal degradation caused by longer signal paths in high-density configurations.
2Adaptability or versatility
If independent access blocks are provided for each array, then array access flexibility improves, but die size and complexity increase
Solution Approach 1:
The patent implements a universal access block design that can service multiple memory arrays through configurable multiplexing. The access block contains programmable decoders and routing logic that can be dynamically configured to access different arrays, providing the flexibility of multiple independent access blocks while using a single shared physical structure, thereby reducing die size and complexity.
Solution Approach 2:
The patent employs dynamic configuration of access block routing and control signals based on the currently active memory array. Control logic dynamically reconfigures the access block parameters and signal paths to match the specific array being accessed, enabling a single access block to adaptively serve multiple arrays with different characteristics.
3Area of stationary object
If signal lines run through other memory arrays, then layout compactness improves, but total resistance along signal lines increases
Solution Approach 1:
The patent utilizes vertical interconnect layers (via holes and interlayer dielectrics) to route signal lines above or below memory arrays rather than through them. This three-dimensional routing approach maintains layout compactness by keeping signal paths within the vertical stack while avoiding the resistive path through array transistors and contacts.
Solution Approach 2:
The patent introduces intermediate signal buffering and regeneration circuits positioned at array boundaries or at regular intervals along long signal lines. These intermediaries detect and re-drive signals, effectively resetting the signal path and compensating for resistance-induced voltage drops, thereby maintaining signal integrity across compact layouts with longer effective signal paths.
Data Source
AI summary
Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to the pair of input/output lines. The first array is configured to provide data to and receive data from the pair of input/output lines. The example apparatus further includes an access block coupled to the pair of input/output lines. The access block is configured to access a second array responsive to memory access control signals directed to the second array. The access block is configured provide data between the second array and the pair of main input/output lines responsive to the access of the second array.