Multi-Memory Controller for Unified Access and Command Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in efficiently controlling operations across different types of memories due to varying access units, burst lengths, and error correction schemes, requiring complex command generation and management to ensure reliable data transfer and storage.
Innovation Solution
A controller system that shares resistors for impedance matching across semiconductor devices, allowing for a chain configuration to generate completion signals and manage data operations based on access units, enabling unified control of volatile and non-volatile memories with diverse characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple types of memories are included in one memory device, then memory functionality and storage capacity are improved, but control complexity increases due to different control schemes required for each memory type
Solution Approach 1:
The controller is designed to universally control multiple types of memories (volatile and non-volatile) through a unified control interface. The controller generates appropriate commands for each memory type based on its characteristics, allowing one controller to manage diverse memory technologies without requiring separate control circuits for each memory type.
Solution Approach 2:
The controller internally segments different control schemes for different memory types while maintaining a unified external interface. Each memory type has its own control logic and command generation mechanism within the controller, allowing independent optimization for each memory type while presenting a uniform control interface to the host system.
2Reliability
If different control schemes are used for various memory types, then operation reliability is improved, but command generation complexity increases
Solution Approach 1:
The controller dynamically selects and applies appropriate control schemes based on the target memory type. The command generation mechanism adapts its behavior according to the memory device being accessed, switching between different control protocols as needed. This dynamic adaptation ensures reliable operation for each memory type while automating the complexity of command generation.
Solution Approach 2:
The controller incorporates feedback mechanisms to monitor the status and characteristics of connected memory devices. Based on this feedback, the controller automatically adjusts its control scheme and command generation strategy to match the specific requirements of each memory type, ensuring reliable operation without manual configuration.
3Speed
If chain-shaped coupling of semiconductor devices is implemented, then signal transmission and completion signaling are improved, but impedance matching complexity increases
Solution Approach 1:
Multiple semiconductor devices are coupled in a chain shape and share a common resistor for impedance matching. By merging the impedance matching function into a shared component, the system reduces the total number of impedance matching elements needed while maintaining proper signal transmission characteristics across the chain of devices.
Solution Approach 2:
The shared resistor acts as an intermediary element that mediates impedance matching for multiple devices in the chain. This intermediary component simplifies the overall impedance matching network by providing a common reference point that all devices in the chain can use, reducing the complexity of individual impedance matching circuits for each device.
Data Source
AI summary
A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.