Multi-Memory Interleaved Data Output for Bandwidth
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Solution Overview
Problem
Memory systems face performance limitations due to increased response times and inefficiencies in data access, particularly when handling multiple read commands, which can result in incorrect or corrupt data output, and existing solutions like increasing data bus bit-width are not feasible for all manufacturers.
Innovation Solution
A multi-memory system that uses interleaved data outputs to provide data efficiently without increasing data bus bit-width, by coordinating the timing of chip enable and output enable signals to allow memories to provide data in an interleaved manner, leveraging the time required for sense operations to complete and optimizing data output during subsequent address accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bit width of a data bus is increased to provide additional bandwidth, then memory bandwidth is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the memory system into multiple independent memory devices, each with its own data bus interface. Instead of using a single wide data bus, the system segments data transmission across multiple narrower buses, allowing parallel access to multiple memory devices while maintaining compatibility with existing devices that cannot be retooled for wider buses.
Solution Approach 2:
The patent transitions from increasing bandwidth through a single dimension (data bus width) to expanding bandwidth through multiple dimensions (multiple memory devices accessed in parallel). This dimensional shift allows bandwidth improvement without increasing the bit-width of individual data bus interfaces.
2Productivity
If read commands are executed at higher frequency, then data output rate is improved, but data corruption occurs due to incomplete sense operations
Solution Approach 1:
The patent initiates sense operations in advance by providing address signals to multiple memory devices before read commands are fully executed. This preliminary action allows sense operations to complete their required duration while the system prepares subsequent read commands, ensuring data integrity is maintained even at higher command frequencies.
Solution Approach 2:
The patent maintains continuous useful action by overlapping sense operations with command execution across multiple memory devices. While one memory device is completing a sense operation, other memory devices are receiving addresses and preparing their sense operations, ensuring that the system continuously provides data without interruption or corruption.
3Measurement precision
If sense operation time is increased to ensure complete data sensing, then data accuracy is improved, but response time increases
Solution Approach 1:
The patent provides address signals to multiple memory devices in advance, allowing sense operations to begin their required duration before read commands are fully executed. This preliminary addressing ensures that when read commands are issued, the sense operations are already underway or complete, maintaining data sensing accuracy without adding to the overall response time.
Solution Approach 2:
The patent uses periodic interleaved read commands distributed across multiple memory devices, where each device receives commands at intervals that allow complete sense operations. This periodic action pattern ensures that each memory device has sufficient time to complete sensing while the system maintains high overall throughput through parallel operation.
4Productivity
If page read execution rate is increased, then productivity is improved, but ability to respond to random read requests deteriorates
Solution Approach 1:
The patent segments the memory system into multiple independent memory devices, each capable of handling different types of read requests. This segmentation allows the system to maintain high page read execution rates on each device while simultaneously accepting and processing random read requests across the distributed memory architecture, improving overall adaptability.
Solution Approach 2:
The patent resolves the contradiction by moving from a single-memory architecture to a multi-memory dimensional architecture. This allows the system to achieve high page read rates through parallel processing across multiple devices while maintaining random request response ability through distributed addressing, effectively adding a spatial dimension to handle different request types simultaneously.
Data Source
AI summary
Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.