Independent Power Mode Control for Multi-Memory Devices
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Solution Overview
Problem
Existing memory systems waste power by operating volatile and non-volatile memory components in synchronized power modes, leading to inefficient energy usage due to mismatched traffic and access expectancies.
Innovation Solution
Implementing a system where the power mode of volatile memory is controlled based on host device commands, and the power mode of non-volatile memory is independently managed based on the quantity of queued commands, allowing for dynamic power adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If volatile and non-volatile memory components operate in synchronized power modes, then system simplicity is maintained, but power consumption increases due to mismatched traffic and access expectancies
Solution Approach 1:
The patent segments the power mode control of volatile and non-volatile memory components, allowing each to be managed independently based on its specific traffic patterns and access requirements. The volatile memory controller and non-volatile memory controller operate autonomously, enabling differentiated power management strategies for each memory type rather than forcing synchronized operation.
Solution Approach 2:
The patent implements dynamic power mode adjustment where the non-volatile memory controller monitors its command queue depth and transitions power modes based on real-time workload conditions. When the queue depth falls below a threshold indicating idle state, the controller transitions to a lower power mode; when queue depth exceeds the threshold indicating active usage, it transitions to a higher power mode.
2Use of energy by moving object
If non-volatile memory transitions to lower power modes when idle, then energy efficiency improves, but responsiveness may deteriorate when commands are needed
Solution Approach 1:
The patent implements a queue depth threshold mechanism that monitors upcoming commands before they are executed. By maintaining a threshold of queued commands, the system ensures that the non-volatile memory remains in higher power modes when work is anticipated, preventing premature transitions to low power modes that would cause latency. This preliminary monitoring of command queues allows the system to proactively maintain responsiveness while still enabling power savings during genuinely idle periods.
3Adaptability or versatility
If volatile memory power mode is controlled by host device commands, then compatibility with host is maintained, but independent optimization of non-volatile memory is limited
Solution Approach 1:
The patent segments the control authority for power mode management between volatile and non-volatile memory components. The volatile memory controller responds to host device commands to maintain compatibility and coordinated operation. Simultaneously, the non-volatile memory controller operates independently, monitoring its own command queue depth and making autonomous power mode decisions based on its specific workload characteristics, thereby enabling independent optimization without sacrificing host compatibility.
Solution Approach 2:
The non-volatile memory controller performs self-service by autonomously monitoring its command queue depth and transitioning power modes based on its own workload conditions rather than relying solely on host device commands. This self-service capability allows the non-volatile memory to optimize its power consumption based on real-time operational needs while the volatile memory continues to respond to host commands for compatibility.
Data Source
AI summary
Methods, systems, and devices for power mode control in a multi-memory device are described. An apparatus may include a non-volatile memory and a volatile memory. The apparatus may operate the volatile memory in a first power mode and the non-volatile memory in a second power mode. The apparatus may transition the volatile memory from the first power mode to a third power mode based on a power mode command from a host device. The apparatus may transition the non-volatile memory from the second power mode to a fourth power mode that consumes less power than the second power mode irrespective of the command from the host device and based on a quantity of queued commands for the non-volatile memory being less than a threshold quantity.