Multi-Memory RAID XOR Processing for Host Load and Bus Congestion
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Solution Overview
Problem
In information processing systems using RAID configurations, data updates and rebuild operations can lead to increased load on the host and congestion in data transfer to specific memory systems, degrading overall system performance due to insufficient bus bandwidth.
Innovation Solution
Implementing an information processing system with a host and multiple memory systems that perform exclusive-logical-OR operations to distribute data updates across memory systems, reducing the load on the host by offloading update operations to the memory systems and preventing data transfer congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data updates are performed in a RAID configuration using conventional methods, then fault tolerance is maintained, but the load on the host increases and data transfer congestion occurs
Solution Approach 1:
The patent extracts the XOR operation functionality from the host CPU and relocates it to dedicated XOR circuitry within the RAID controller. This extraction removes the computational burden from the host, allowing fault tolerance operations to proceed without degrading host performance or causing data transfer congestion.
Solution Approach 2:
The patent introduces an intermediary RAID controller with built-in XOR circuits that mediates between the host and memory systems. This intermediary handles the computationally intensive XOR operations locally, preventing both host overload and bus congestion while maintaining RAID fault tolerance capabilities.
2Manufacturing precision
If data updates are performed by the host in conventional RAID systems, then data consistency is maintained, but bus bandwidth is insufficient and performance degrades
Solution Approach 1:
The patent extracts the XOR computation task from the host and relocates it to the RAID controller's dedicated XOR circuits. This extraction enables data consistency to be maintained through local computation at the controller, eliminating the need for high bus bandwidth and preventing performance degradation.
Solution Approach 2:
The patent replaces the mechanical/computational burden on the host bus with dedicated hardware XOR circuits in the RAID controller. This substitution moves the computational workload from the host system to the storage subsystem, maintaining data consistency while eliminating bus bandwidth constraints.
Data Source
AI summary
According to one embodiment, an information processing system includes a host and memory systems. A first memory system stores first data in a nonvolatile memory. A second memory system stores second data in a nonvolatile memory. The host transmits first update data to the first memory system and transmits second update data to the second memory system. The first memory system generates first XOR data by performing an XOR operation on at least the first data and the first update data, and transmits the first XOR data to the second memory system. The second memory system generates second XOR data by performing an XOR operation on the second data, the second update data, and the first XOR data, and transmits the second XOR data to a third memory system.