Multi-metal dipole doping for CMOS threshold voltage tuning
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Solution Overview
Problem
Current methods for tuning threshold voltage (Vt) in semiconductor devices, such as channel doping and multi-layer metal gate methods, face challenges like device performance degradation, manufacturability issues, and incompatibility with advanced device architectures like GAA FETs and VTFETs, particularly due to interfacial layer regrowth problems associated with multiple anneal cycles.
Innovation Solution
The integration of a dipole first patterning scheme and a dipole last patterning scheme before annealing, which forms multiple pairs of Vt devices without the interfacial layer regrowth issue, using a stack structure with different thicknesses of dipole layers and sacrificial layers to achieve various Vt pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel doping is used to tune threshold voltage, then threshold voltage can be adjusted, but device performance degrades and manufacturability is compromised
Solution Approach 1:
The patent extracts the threshold voltage tuning function from the channel doping process and relocates it to the gate stack structure. By removing dopants from the channel region and concentrating the Vt control mechanism in the gate electrode and interfacial layers, the method eliminates performance degradation while preserving manufacturing precision.
Solution Approach 2:
The patent introduces an interfacial layer between the semiconductor channel and the gate dielectric as an intermediary element for threshold voltage control. This interfacial layer, with its specific thickness and composition, acts as a mediator that enables precise Vt tuning without the harmful effects of channel doping, thereby improving both device performance and manufacturability.
2Adaptability or versatility
If multiple anneal cycles are performed for multi-layer metal gate processing, then multiple Vt pairs can be achieved, but interfacial layer regrowth occurs
Solution Approach 1:
The patent performs preliminary actions by forming the complete multi-layer gate stack structure and establishing all necessary interfaces before performing any annealing cycles. The gate electrodes, dielectric layers, and interfacial layers are all prepared in their final configurations prior to thermal processing, preventing interfacial regrowth while enabling multi-Vt functionality.
Solution Approach 2:
The patent segments the threshold voltage control into multiple independent layers within the gate stack, with each layer contributing to a specific Vt pair. This segmentation allows different regions of the gate stack to be optimized for different Vt requirements without requiring multiple anneal cycles that would cause interfacial regrowth.
3Manufacturing precision
If conventional multi-layer metal gate methods are used, then threshold voltage can be tuned, but compatibility with advanced device architectures like GAA FETs and VTFETs is lost
Solution Approach 1:
The patent creates a universal gate stack structure that can be applied to multiple device architectures including planar FETs, GAA FETs, and VTFETs. The multi-layer gate configuration with controlled interfacial layers provides a platform that delivers threshold voltage tuning capability across different device types without requiring architecture-specific modifications.
Data Source
AI summary
A method for fabricating a semiconductor device including multiple pairs of threshold voltage (Vt) devices includes forming a stack on a base structure having a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices and a third region corresponding to a third pair of Vt devices. The stack includes a first dipole layer, a first sacrificial layer formed on the first dipole layer, a second sacrificial layer formed on the first sacrificial layer, and a third sacrificial layer formed on the second sacrificial layer. The method further includes forming a second dipole layer different from the first dipole layer.