Multi-Metal Gate Via Fill for Void-Free Nanosheet FET Contacts
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Solution Overview
Problem
In advanced semiconductor technology nodes, dimension scaling poses challenges in forming contacts and vias to gate, source, and drain electrodes of field-effect transistors, leading to voids in gate vias and degraded contact resistance due to the use of different metal materials for metallization.
Innovation Solution
An efficient metal gap fill method is implemented using two different metal liners and bulk fill metal for improved gate via fill quality, and the same metal material is used for source/drain vias and metallization to minimize contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dimension scaling is performed to increase functional density, then production efficiency is improved and costs are lowered, but manufacturing complexity increases and voids form in gate vias
Solution Approach 1:
The gate via fill process is segmented into multiple sequential steps: first forming a metal liner layer (e.g., tungsten or cobalt) conformally on the via walls, then filling the remaining void with a different bulk fill metal (e.g., copper or aluminum). This segmentation allows each metal to perform its optimal function - the liner provides adhesion and prevents void formation, while the bulk fill provides low resistance
Solution Approach 2:
Different regions of the gate via are assigned different metal materials based on their specific functional requirements. The via wall region receives a metal liner with high adhesion properties to prevent void formation, while the via center receives bulk fill metal with low electrical resistance. This local differentiation of material properties resolves the contradiction between maintaining via integrity and achieving low resistance
2Reliability
If different metal materials are used for metallization, then device performance can be optimized, but contact resistance increases due to material interfaces
Solution Approach 1:
A metal liner layer acts as an intermediary between the bulk fill metal in the via and the overlying metallization layers. This intermediate layer is specifically designed to provide good adhesion to both materials and maintain low contact resistance across the interface, thereby resolving the contradiction between using different metals for performance optimization and maintaining low contact resistance
3Quantity of substance
If dimension scaling continues, then functional density increases, but void formation in gate vias degrades device performance
Solution Approach 1:
The metal liner layer is formed preliminarily before the bulk fill metal deposition. This preliminary action of lining the via walls with an adherent metal layer prevents void formation during subsequent processing steps and ensures complete, void-free filling of the via, thereby maintaining device performance as dimensions are scaled down
Data Source
AI summary
A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.