Multi-Metal Contact Structure for Low-Dishing Interconnects
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Solution Overview
Problem
The damascene process in semiconductor chip fabrication leads to 'dishing' defects in metal pattern density features and large metal structures during chemical mechanical polishing, resulting in poor flatness and defective bonds, which reduces device yield and complicates mask design.
Innovation Solution
A multi-metal contact structure is introduced, comprising a softer conductive material for the mesh and a harder conductive material for the fill, which reduces dishing and enhances conductivity by increasing the electrically conductive area, while allowing for improved bonding at lower annealing temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing is used to planarize the substrate surface, then flatness is improved, but dishing defects occur in metal pattern density features and large metal structures
Solution Approach 1:
The patent applies local quality by using a multi-metal contact structure where different metal regions have different properties. Specifically, the contact structure includes a first metal region with different polishing characteristics than a second metal region, allowing each region to be optimized for its specific function while resisting uniform dishing across the entire contact area during chemical mechanical polishing
Solution Approach 2:
The patent employs composite materials by creating a contact structure composed of multiple metal types with different mechanical and electrical properties. This multi-metal composite structure combines metals with varying hardness, conductivity, and polishing rates to achieve overall resistance to dishing while maintaining electrical conductivity and bonding capability
2Reliability
If large metal structures are used in the contact area, then conductivity is improved, but dishing defects increase
Solution Approach 1:
The patent applies segmentation by dividing the contact structure into multiple metal regions with different properties. The contact area is segmented into a first metal region and a second metal region, each contributing differently to conductivity and polishing behavior, thereby maintaining overall conductivity while reducing dishing through the combined structure
Solution Approach 2:
The patent uses parameter changes by varying the material composition, hardness, and electrical conductivity parameters across different regions of the contact structure. By changing these parameters spatially within the contact area, the patent achieves optimized conductivity in high-current regions while using harder, more polishing-resistant materials in regions prone to dishing
3Manufacturing precision
If dummy dielectric features are incorporated to reduce dishing, then surface flatness is improved, but mask design complexity increases
Solution Approach 1:
The patent applies the taking out principle by removing the dummy dielectric features from the structure and replacing them with a multi-metal contact structure. This extraction eliminates the need for complex mask designs associated with dummy features while maintaining dishing resistance through the inherent properties of the multi-metal construction
Solution Approach 2:
The patent applies inversion by reversing the conventional approach: instead of adding dummy dielectric features to reduce dishing, the patent uses a multi-metal contact structure where the metal composition itself is engineered to resist dishing. This inverted approach simplifies mask design by eliminating the need for dummy feature patterning
Data Source
AI summary
A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.