Multi-Mode ADC Architecture for High-Resolution Image Sensors
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Solution Overview
Problem
Current analog-to-digital converters (ADCs) and image sensors face challenges in achieving high-resolution and high-speed operations with a wide dynamic range, limiting their ability to accurately convert analog image signals into digital signals efficiently.
Innovation Solution
The proposed solution involves a multi-mode ADC configuration with upper, lower, and delta-sigma converters that operate in successive approximation, oversampling, and delta-sigma modes to generate upper and lower bit values, effectively narrowing the input signal range and amplifying residue signals to enhance resolution and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional ADC is used for image signal conversion, then the device structure is simple, but the resolution and dynamic range are limited
Solution Approach 1:
The ADC is divided into multiple independent converters, each responsible for converting a specific bit range of the input signal. This segmentation allows each converter to operate with simplified logic while collectively achieving high-resolution conversion, resolving the contradiction between measurement precision and device complexity.
Solution Approach 2:
The patent introduces a time dimension by operating converters in different time slots or modes. Multiple converters process different portions of the signal spectrum at different times, effectively increasing the conversion resolution without proportionally increasing the simultaneous circuit complexity.
2Measurement precision
If oversampling is performed multiple times to increase resolution, then the conversion precision improves, but the operation speed decreases
Solution Approach 1:
The signal processing is segmented into parallel paths where different converters handle different bit ranges simultaneously. This parallel segmentation achieves high conversion precision without requiring sequential oversampling, thereby maintaining high operation speed.
Solution Approach 2:
Instead of performing complete oversampling cycles for all bits, the patent applies partial action by having different converters process different portions of the signal. This reduces the total processing time while achieving the required precision through coordinated partial conversions.
3Adaptability or versatility
If the input signal range is widened to increase dynamic range, then the adaptability improves, but the conversion precision for specific ranges decreases
Solution Approach 1:
The wide input signal range is segmented into multiple sub-ranges, with each converter optimized for a specific sub-range. This segmentation maintains high conversion precision within each sub-range while collectively covering a wide dynamic range, resolving the contradiction between adaptability and precision.
Solution Approach 2:
Each converter is designed with local quality optimization, where the conversion logic and reference signals are tailored to the specific characteristics of its assigned signal range. This ensures high precision for local ranges while the system as a whole achieves wide dynamic range coverage.
Data Source
AI summary
An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.