Multi-mode Bit Rate Processor for Wireless Standards
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Solution Overview
Problem
Current wireless communication systems face challenges in efficiently processing and adapting to various data transmission standards and channel specifications, particularly in handling multiple modes and transmission rates, which affects data transmission quality and system capacity.
Innovation Solution
A multi-mode bit rate processor is designed to selectively use sub-modules based on data and transmission channel specifications, including de-modulation, de-scrambling, de-rate matching, and channel decoding, to process signals for standards like TD-SCDMA, HSDPA, and WCDMA, optimizing memory organization and reducing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a processor supports multiple data transmission standards and modes, then adaptability is improved, but device complexity increases
Solution Approach 1:
The processor is divided into multiple functional sub-modules including de-interleaving sub-modules, rate matching sub-modules, channel decoding sub-modules, and de-modulation sub-modules. Each sub-module handles specific processing tasks for different transmission standards, allowing the system to support multiple standards (TD-SCDMA, WCDMA, HSDPA) while keeping each module's complexity manageable through specialized function division.
Solution Approach 2:
The processor design incorporates universal sub-modules that can handle multiple transmission standards through configurable parameters and adaptive selection mechanisms. The de-interleaving sub-module, rate matching sub-module, and channel decoding sub-module are designed to process different channel types (dedicated channels, common channels, shared channels) and standards (Release 4, HSDPA) using the same hardware structure with adjustable parameters, reducing overall device complexity while maintaining multi-standard support.
2Adaptability or versatility
If all processing modules are always active to handle any standard, then adaptability is improved, but energy consumption increases
Solution Approach 1:
The processor implements dynamic module selection where sub-modules are adaptively enabled or disabled based on the detected transmission standard and channel type. The control logic dynamically configures the processor to activate only the necessary sub-modules for the current transmission mode (e.g., activating HSDPA-specific rate matching sub-modules only when processing HSDPA traffic), thereby reducing energy consumption while maintaining full adaptability across different standards.
3Adaptability or versatility
If memory is organized to accommodate all channel types, then adaptability is improved, but memory complexity increases
Solution Approach 1:
The memory system is organized with different memory regions optimized for specific channel types and transmission standards. Dedicated memory areas are allocated for dedicated channels (DCH), common channels (BCH, FACH, PCH, RACH, CPCH), and shared channels (DSCH, HS-DSCH), with each region having tailored access patterns and organization structures. This local optimization allows the memory system to efficiently support multiple channel types without requiring a single complex unified structure.
Data Source
AI summary
An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.