Multi-Mode Compression Acceleration for Memory Bottlenecks
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Solution Overview
Problem
Conventional data accelerators in digital computer systems face increased workload and memory bottlenecks when performing data compression with high compression ratios, limiting their efficiency and scalability.
Innovation Solution
A multi-mode hardware accelerator that selectively operates in synchronous and asynchronous modes, utilizing the same processor for synchronous compression and multiple processors for asynchronous compression to distribute processing work and reduce memory consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional data accelerator is used to perform data compression with high compression ratios, then compression capability is improved, but memory consumption increases and pipeline bottlenecks occur
Solution Approach 1:
The patent segments the data compression workload across multiple processors instead of concentrating it in a single accelerator. The system divides the data stream into multiple chunks and distributes them to different processors, thereby reducing the memory burden on any single component while maintaining high compression capability through parallel processing.
Solution Approach 2:
The patent implements a nested architecture where hardware accelerators are integrated within a multi-processor system. The accelerators operate as nested components within the broader parallel processing framework, allowing them to provide acceleration for specific compression tasks while the overall system manages memory distribution across multiple processors to avoid bottlenecks.
2Productivity
If more hardware accelerators are incorporated onto a single chip to improve compression throughput, then processing speed is improved, but area and logic resource requirements increase
Solution Approach 1:
The patent makes the processor system universal by enabling it to perform both general-purpose computing and specialized data compression tasks. The multi-processor system can dynamically allocate resources for compression workloads, making the same hardware infrastructure serve multiple functions and reducing the need for dedicated compression hardware that would consume additional chip area.
Solution Approach 2:
The patent merges the data compression functionality with the existing multi-processor system architecture. Instead of adding separate dedicated compression accelerators that would increase chip area, the system combines compression capabilities with the general-purpose processors, allowing them to handle both computation and compression tasks efficiently.
3Device complexity
If a single processor is used to run applications and perform compression, then device complexity is reduced, but processing speed decreases due to workload concentration
Solution Approach 1:
The patent segments the processing workload across multiple processors, dividing the data stream into parallel processing channels. This segmentation increases processing speed by utilizing multiple processing units simultaneously while keeping the system architecture relatively simple through standardized inter-processor communication interfaces and coordinated task distribution.
Data Source
AI summary
A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.