Multi-Mode Data Shifting Circuit for Variable QC-LDPC Data Widths
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Solution Overview
Problem
In high-speed communication systems, quasi-cyclic low density parity check (QC-LDPC) decoders require multiple shifting circuits to handle different data amounts, leading to increased control complexity, hardware cost, and reduced operation efficiency due to the need for separate circuits for each data amount.
Innovation Solution
A data shifting operation apparatus and method using a preprocessing circuit, two shifting circuits, and a multiplexer to cyclically shift data, allowing support for various data amounts with a single configuration, reducing hardware complexity and cost by calculating and applying total shift amounts based on the difference between maximum and desired data amounts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple shifting circuits are used to handle different data amounts, then data shifting operation for various data amounts is supported, but hardware cost and device complexity increase greatly
Solution Approach 1:
The patent applies universality by designing a single shifting circuit that can handle multiple data amounts through configurable parameters. Instead of having separate shifting circuits for each data amount, one shifting circuit is designed to be universally applicable by adjusting control signals and shift amounts, thereby supporting various data amounts while reducing hardware complexity
Solution Approach 2:
The patent utilizes parameter changes by modifying the shift amount parameter and control signals based on the desired data amount. The shifting circuit responds to different parameter configurations (shift amounts, control signal values) to adapt its behavior, enabling the same hardware to perform different data shifting operations for various data amounts without physical reconfiguration
2Adaptability or versatility
If multiple shifting circuits are used to handle different data amounts, then all data amounts are supported, but control complexity increases greatly
Solution Approach 1:
The control mechanism is designed to be universal by using a standardized control interface that works for all data amounts. A single control unit generates appropriate control signals for the shifting circuit based on the desired data amount, eliminating the need for separate control logic for each data amount and thereby reducing control complexity
3Adaptability or versatility
If multiple shifting circuits are used to handle different data amounts, then data shifting for each data amount is enabled, but critical path delay increases
Solution Approach 1:
The patent merges multiple shifting operations into a single shifting circuit, combining the functionality of what would otherwise be separate circuits. This consolidation eliminates the need for multiple parallel shifting paths, reducing the critical path delay by ensuring that only one shifting operation needs to complete for any given data amount
Data Source
AI summary
The present disclosure provides a data shifting operation apparatus having multiple operation modes that includes a preprocessing circuit, a first and a second shifting circuits and a multiplexer. The preprocessing circuit stores an input data group, having a data amount equal to a desired data amount M, to an under-operation data group, having the data amount equal to a maximum usage data amount N, from a most significant bit, and receives a shift amount S to calculate a total shift amount. The first and the second shifting circuits respectively cyclically shift the under-operation data group for the shift amount and the total shift amount to generate a first and a second shifted data groups. The multiplexer selects S data from the most significant bit of the second shifted data group and (M−S) data from the (N−S)-th bit of the first shifted data group to output a final shifted data group.