Multi-Mode RAM for Display Drivers Without External Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display drivers require external conversion circuits and increased area due to the need for different RAMs to support vertical and horizontal write modes, leading to longer clock cycles and higher current consumption.
Innovation Solution
A storage device with a memory cell array that can be accessed in both vertical and horizontal write modes without an external conversion circuit, using a write circuit to write pixel data units for pixels on the same data line or scan line, and a read circuit to select and read out data accordingly, allowing for bit line selection processing based on the write mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conversion circuit is provided externally to the RAM to perform serial/parallel conversion for vertical and horizontal write modes, then the RAM can be accessed in both modes, but the device complexity increases and current consumption increases
Solution Approach 1:
The patent makes the RAM itself multi-functional by enabling it to directly accept both vertical write mode data (multiple pixels on same data line, different scan lines) and horizontal write mode data (multiple pixels on same scan line, different data lines) without requiring external conversion circuits. The RAM's memory cell array and decode circuits are designed to handle both data organization formats natively, eliminating the need for separate serial/parallel conversion circuits and reducing overall device complexity.
Solution Approach 2:
The RAM performs its own data conversion function internally through its decode circuits and memory cell array structure. Instead of relying on external conversion circuits to prepare data before it reaches the RAM, the RAM's internal architecture automatically handles the organization of data in both vertical and horizontal write modes, making the conversion function self-contained within the RAM itself.
2Adaptability or versatility
If a conversion circuit is provided externally to the RAM, then the RAM can be accessed in both vertical and horizontal write modes, but the current consumption increases
Solution Approach 1:
The patent extracts the data conversion function from external conversion circuits and integrates it directly into the RAM's internal architecture. By removing the need for separate external conversion circuits, the patent eliminates the additional current consumption that would be required to operate those external circuits, while still maintaining the capability to handle both vertical and horizontal write modes through the RAM's own decode circuits and memory cell array.
3Adaptability or versatility
If two types of RAMs (first RAM for vertical write mode and second RAM for horizontal write mode) are provided, then the RAM can be accessed in both modes, but the area occupied by the RAMs increases
Solution Approach 1:
The patent merges the functionality of what would traditionally require two separate RAMs (one optimized for vertical write mode and another for horizontal write mode) into a single unified RAM structure. The memory cell array and decode circuits are designed to natively support both data organization formats, allowing one RAM to perform the work of two while occupying only the area of one, thereby reducing the overall area required.
Solution Approach 2:
The single RAM is designed with universal capability to handle both vertical and horizontal write modes through its memory cell array and decode circuit architecture. This multi-functional design eliminates the need for dual-RAM configurations, reducing the total area occupied while maintaining full compatibility with both write modes.
4Quantity of substance
If display data is written into the RAM in units of 8 bits with 8 times longer clock cycle, then the RAM can process the data, but a clock generation circuit needs to be provided
Solution Approach 1:
The patent applies preliminary organization of display data into appropriate units (either 8 pixels on the same data line for vertical mode or 8 pixels on the same scan line for horizontal mode) before writing to the RAM. This preliminary organization allows the RAM to process data in its native format without requiring extended clock cycles or additional clock generation circuits, as the data is already structured for direct loading into the memory cell array.
Data Source
AI summary
A write circuit of a storage device, in a first mode, writes a plurality of first pixel data units, each of the first pixel data units being constituted by data for pixels that are on the same data line and on different scan lines in a display panel, into a plurality of memory cells connected to a selected word line, and in a second mode, writes a plurality of second pixel data units, each of the second pixel data units being constituted by data for pixels that are on the same scan line and on different data lines in the display panel, into a plurality of memory cells connected to a selected word line.