Multi-Mode DLL Circuit for Fast Locking and Low Jitter
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Solution Overview
Problem
Current delay-locked loop (DLL) circuits in high-speed DRAM face issues with data jittering and current variation due to fixed update frequencies and steps, leading to incorrect data reading and increased power consumption, especially during mode transitions like refreshing and reading.
Innovation Solution
A DLL circuit with multiple modes that dynamically adjusts its update frequency and delay step based on external commands, allowing quick delay locking and reduced jittering during data reading, and lower power consumption during standby.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the counting control circuit uses a fixed update frequency and delay step, then the circuit structure is simple, but the delay locking speed is slow and cannot adapt quickly to large changes of delay
Solution Approach 1:
The counting control circuit is designed with two operable modes that can be dynamically switched between. The first mode has a first update frequency and first delay step, while the second mode has a second update frequency and second delay step. This dynamic configurability allows the system to adapt the update frequency and delay step according to different operational requirements, thereby improving delay locking speed without permanently increasing circuit complexity.
Solution Approach 2:
The patent changes the parameters of the counting control circuit by providing two distinct modes with different update frequencies and delay steps. The controller can select between these modes to optimize performance. This parameter variation allows the system to achieve faster delay locking when needed while maintaining simpler operation during normal conditions, effectively resolving the contradiction between speed and complexity.
2Reliability
If the DLL circuit uses consecutive auto-refresh commands, then the memory refresh function is performed, but the current consumption increases significantly causing internal power supply voltage changes and output signal negative delay
Solution Approach 1:
The counting control circuit can dynamically switch between two modes based on the operational state of the DLL circuit. During memory refresh operations, the circuit can operate in a mode optimized for refresh reliability. During normal data reading operations, it can switch to a mode with lower current consumption, thereby reducing power supply voltage fluctuations and preventing output signal negative delay while maintaining refresh reliability when required.
3Reliability
If the counting control circuit has a fixed period and step, then the circuit design is straightforward, but it cannot reduce delay jittering during data reading operations
Solution Approach 1:
The counting control circuit is designed with two operable modes that can be dynamically switched. The controller selects the appropriate mode based on the current operation type (refresh or data reading). This dynamic switching capability allows the system to optimize for data reading accuracy by using the mode with appropriate update frequency and delay step characteristics during reading operations, while maintaining straightforward design principles through the modular two-mode structure.
4Speed
If the DLL circuit operates in high-speed mode for quick delay locking, then the locking speed is improved, but the delay jittering increases during data reading
Solution Approach 1:
The counting control circuit dynamically switches between two modes based on operational requirements. During the delay locking phase, the circuit operates in the mode with higher update frequency to achieve quick locking. Once locking is achieved and during data reading operations, it switches to the mode with lower update frequency to reduce delay jittering and improve reading stability. This dynamic adaptation resolves the contradiction between locking speed and reading stability.
Solution Approach 2:
The system uses periodic switching between two operational modes. The first mode with higher update frequency is applied periodically during delay locking to achieve fast convergence. The second mode with lower update frequency is applied periodically during data reading to maintain stability. This periodic action between modes allows the system to optimize performance for each operational phase, resolving the contradiction between fast locking and stable reading.
Data Source
AI summary
A DLL circuit comprising a delay circuit, a phase detector and a counting control circuit. The delay circuit is configured to receive a reference clock signal, and delay the reference clock signal to output a delayed clock signal. The phase detector is configured to detect a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal. The counting control circuit is configured to generate a control delay signal according to the phase difference signal. The delay circuit delays the reference clock signal according to the control delay signal to output the delayed clock signal. When the counting control circuit is in the first mode, the counting control circuit has a first update frequency. When the counting control circuit is in the second mode, the counting control circuit has a second update frequency.