Multi-Mode FPGA Device for Dynamic Storage and Acceleration Provisioning
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Solution Overview
Problem
Current solutions for deploying direct-attached devices in data centers are inefficient due to limited scalability, high cost, and power inefficiency of CPU links, which restricts the performance and deployment of SSDs and hardware accelerators.
Innovation Solution
A system and method that creates a distributed cluster of PCIe links within a server or expansion unit, utilizing NVMe for parallelism and dynamic provisioning across high-performance interconnects like PCIe, Omnipath, and 100 GbE, allowing for flexible configuration and mode switching to optimize performance and extend device lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct-attached devices are deployed using CPU links, then high throughput and low latency are achieved, but scalability is limited and cost and power consumption increase
Solution Approach 1:
The system segments the monolithic CPU-attached device model into distributed PCIe link segments that can be independently configured and combined. Multiple PCIe links are divided into separate configurable units that can be dynamically allocated to different devices, enabling scalable deployment while maintaining high-performance direct-attached characteristics for each segment.
Solution Approach 2:
The PCIe link configuration system provides universal functionality by enabling the same PCIe infrastructure to serve multiple different device types and performance requirements. The configurable nature of PCIe links allows them to be adapted for various storage devices, accelerators, and other peripherals, replacing the need for dedicated CPU links for each device type.
2Speed
If direct-attached devices are deployed using CPU links, then high performance is achieved, but deployment cost and power consumption increase
Solution Approach 1:
The system extracts the high-performance direct-attachment capability from the CPU core and relocates it to the PCIe link layer. This allows performance-critical paths to use direct PCIe connections while the CPU is freed from managing individual device attachments, reducing overall system power consumption and enabling more efficient resource sharing.
3Quantity of substance
If devices are deployed at large scale in data centers, then capacity is increased, but efficiency decreases due to limited CPU links and external switching network requirements
Solution Approach 1:
The system merges multiple PCIe links into unified configurable channels that can be dynamically allocated to different devices. This consolidation eliminates the need for separate external switching networks for each device connection, improving deployment efficiency while supporting large-scale device capacity through aggregated PCIe resources.
4Speed
If PCIe links are configured for specific devices, then performance is optimized, but adaptability to different application needs decreases
Solution Approach 1:
The PCIe link configuration is made dynamic and reconfigurable, allowing the system to adapt link allocations based on different application requirements. Performance can be optimized for specific devices when needed, while the same infrastructure can be reconfigured for different applications, maintaining both performance optimization and adaptability through time-varying configurations.
Data Source
AI summary
The invention is an apparatus for dynamic provisioning available as a multi-mode device that can be dynamically configured for balancing between storage performance and hardware acceleration resources on reconfigurable hardware such as an FPGA. An embodiment of the invention provides a cluster of these multi-mode devices that form a group of resilient Storage and Acceleration elements without requiring a dedicated standby storage spare. Yet another embodiment of the invention provides an interconnection network attached cluster configured to dynamically provision full acceleration and storage resources to meet an application's needs and end-of-life requirements of an SSD.