Multi-Mode LO PLL Architecture for Fast TX/RX Frequency Switching
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuitry in wireless communication devices faces challenges in generating independent transmit and receive local oscillator signals while maintaining stability and switching speed, especially when multiple frequencies are involved, leading to limitations in frequency selection and switching speed.
Innovation Solution
A three-PLL structure is implemented, where a reference PLL generates signals for two independent PLLs, one for the receiver and one for the transmitter, allowing each to operate at different frequencies and switch rapidly without compromising stability, with dividers adjusting the frequency division to accommodate various communication protocols like GSM/EDGE and WCDMA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single PLL is used to generate both transmit and receive local oscillator signals, then device complexity is reduced, but frequency selection flexibility and switching speed are limited
Solution Approach 1:
The patent divides the single PLL function into three separate PLL circuits: a reference PLL, a transmit PLL, and a receive PLL. This segmentation allows each PLL to be independently optimized for its specific function, enabling flexible frequency selection and rapid switching for both transmit and receive operations while maintaining overall system coordination through the reference PLL.
Solution Approach 2:
The reference PLL serves multiple functions by providing reference signals to both the transmit PLL and receive PLL. This multi-functionality allows the system to maintain frequency coherence across different communication modes (transmit and receive) while still benefiting from independent frequency control through the separate PLL circuits.
2Adaptability or versatility
If separate PLLs are used for transmit and receive paths, then frequency selection flexibility is improved, but device complexity increases
Solution Approach 1:
The system is segmented into three specialized PLL circuits, each handling specific frequency generation tasks. This segmentation provides the frequency selection flexibility needed for different communication protocols while organizing the complexity into manageable, functionally distinct modules.
Solution Approach 2:
The reference PLL acts as an intermediary that coordinates between the transmit and receive PLLs. It provides synchronized reference signals that enable independent frequency control in transmit and receive paths while maintaining overall system coherence, thus managing complexity through centralized coordination.
3Device complexity
If a single PLL switches between multiple frequencies, then device complexity is reduced, but switching speed is compromised
Solution Approach 1:
By segmenting the frequency generation into three dedicated PLL circuits, each PLL can be optimized for its specific frequency range and switching requirements. The transmit PLL and receive PLL can switch frequencies independently and simultaneously without the delays inherent in a single PLL switching between multiple frequencies, thus improving switching speed.
Solution Approach 2:
The reference PLL generates reference signals in advance that are used by both the transmit and receive PLLs. This preliminary action allows the transmit and receive PLLs to be pre-configured with their respective frequency requirements, enabling rapid frequency switching without waiting for reconfiguration from a single shared PLL.
4Adaptability or versatility
If frequency division is used to accommodate multiple protocols, then adaptability to different communication standards is improved, but manufacturing precision requirements increase
Solution Approach 1:
The reference PLL serves as a precision intermediary that provides highly accurate reference signals to both the transmit and receive PLLs. This intermediary role ensures that frequency division operations in the transmit and receive paths maintain high precision, accommodating multiple communication protocols while meeting stringent manufacturing tolerance requirements.
Solution Approach 2:
The phase-locked loop architecture inherently provides feedback control that continuously monitors and corrects frequency division accuracy. This feedback mechanism ensures that even with variations in manufacturing precision, the system maintains accurate frequency relationships required for multiple communication protocols.
Data Source
AI summary
A local oscillator (LO) signal generator that has a reference phase-locked loop (PLL), a receiver LO PLL and a transmitter LO PLL. A reference PLL is coupled to receive a reference clock input and to generate a reference PLL signal at its output, which then drives a receiver PLL and a transmitter PLL. The receiver PLL is coupled to receive the reference PLL signal and to use the reference PLL signal as its reference input to generate a receiver LO signal at its output. The transmitter PLL is coupled to receive the reference PLL signal and to use the reference PLL signal as its reference input to generate a transmitter LO signal at its output.