Multi-Mode Logic Cells for PLD Routing and Timing Constraints

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Solution Overview

Problem

Programmable logic devices (PLDs) face limitations in programmable logic block (PLB) utilization due to excessive routing resource requirements, which consume a significant portion of area, power, and timing budget, restricting the flexibility and efficiency of user designs.

Innovation Solution

Implementing multiple mode or convertible logic cells that can operate in different operational modes, such as logic function, ripple arithmetic, and RAM modes, with combined FS and OFX ports into a single 'FSX' port to reduce the number of necessary ports and simplify routing, along with flexible register placement to optimize PLD components and reduce propagation delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If routing resources are increased to improve PLB utilization, then logic block utilization is improved, but area consumption increases

Engineering Contradiction:

ImprovePLB utilizationVSAvoidrouting resource area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The logic cell is designed to perform multiple functions including logic operations, arithmetic operations, and memory functions through configurable elements. This multi-functionality allows the same routing infrastructure to serve multiple purposes, reducing the need for dedicated routing resources for each function type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines FS and OFX ports into a single FSX port, merging previously separate routing paths. This consolidation reduces the total number of routing resources required while maintaining the ability to perform both logic and arithmetic operations, thereby improving PLB utilization without proportionally increasing area.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If routing resources are increased to improve PLB utilization, then logic block utilization is improved, but power consumption increases

Engineering Contradiction:

ImprovePLB utilizationVSAvoidrouting power consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The configurable logic cell can be programmed to perform different functions (logic, arithmetic, memory) using the same physical routing infrastructure. This universality means that routing resources are not continuously active for all functions simultaneously, reducing overall power consumption compared to having dedicated routing for each function type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

By merging FS and OFX ports into FSX, the patent reduces the number of active routing paths required. Fewer routing paths mean fewer switches and multiplexers actively managing signals, which directly reduces dynamic power consumption in the routing infrastructure.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If routing resources are increased to improve PLB utilization, then logic block utilization is improved, but timing budget is exceeded

Engineering Contradiction:

ImprovePLB utilizationVSAvoidrouting propagation delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The consolidation of FS and OFX ports into a single FSX port reduces the number of routing hops and switching elements that signals must traverse. This shorter routing path directly reduces propagation delay, allowing higher PLB utilization without exceeding the timing budget.

Inventive Principle:

Principle #5Merging (Combining)

4Device complexity

If the number of ports is reduced to simplify routing, then routing complexity is reduced, but functionality is limited

Engineering Contradiction:

Improverouting complexityVSAvoidoperational modes

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The logic cell employs dynamic configuration through mode logic and multiplexers that can switch between different operational modes (logic, arithmetic, memory) based on control signals. This dynamic reconfigurability allows a reduced number of physical ports to support multiple functional modes, maintaining versatility while simplifying routing.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The single FSX port serves multiple functions by being selectively connected to different internal logic paths based on the operational mode. This universal port design eliminates the need for separate dedicated ports for each function, reducing routing complexity while preserving full operational versatility through intelligent signal routing and mode selection.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10630269B2Multiple mode device implementation for programmable logic devices

Publication Date: 2020.04.21 LATTICE SEMICON CORP

AI summary

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.