Multi Mode Modulator Dynamic Load Regulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power converters, such as PWM-PFM dual mode modulators, face inefficiencies in power conversion and dynamic load regulation, particularly at low load currents, where they experience transient output voltage dips during mode transitions, which can be detrimental to sensitive electronic devices.
Innovation Solution
A multi-mode modulator system that includes a PWM modulator with a feedback control loop, a non-pulse width modulation (NPWM) modulator, and a mode selector with mechanisms like dynamic frequency boosting, slew rate boosting, and a dynamic turn-off logic circuit to shorten the NPWM-to-PWM mode transition period, ensuring improved dynamic load regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the prior art PWM-PFM dual mode modulator operates in PFM mode at low load current to save energy, then power conversion efficiency is improved, but dynamic load regulation deteriorates due to transient output voltage dips during mode transition
Solution Approach 1:
The patent applies preliminary action by pre-charging the output capacitor COUT through the low-side power FET before switching from PFM to PWM mode. This preparatory charging action ensures that when the mode transition occurs, the output voltage does not experience significant dips, thus maintaining dynamic load regulation while preserving the energy efficiency benefits of PFM operation at low loads
Solution Approach 2:
The patent implements dynamics by making the low-side power FET switching behavior adaptive based on the operating mode. During PFM-to-PWM transition, the low-side FET is dynamically controlled to remain on longer than usual to charge COUT, whereas in normal operation it follows standard switching timing. This dynamic adjustment resolves the contradiction between efficiency and regulation performance
2Reliability
If the PWM modulator is powered on during PFM-to-PWM mode transition, then dynamic load regulation is improved, but power loss increases due to extended modulator startup time
Solution Approach 1:
The patent extracts the output voltage regulation function from the PWM modulator startup process. By using the low-side power FET to directly charge the output capacitor COUT during mode transition, the system bypasses the need for the PWM modulator to fully initialize and regulate the output voltage during startup, thereby reducing the startup time and associated power losses while still achieving proper voltage regulation
3Reliability
If the output capacitor COUT is increased to reduce output voltage dip, then dynamic load regulation is improved, but device complexity and cost increase
Solution Approach 1:
The patent changes the operational parameters of the low-side power FET during mode transition rather than changing the physical size of COUT. By adjusting the FET switching timing and keeping it conductant longer during PFM-to-PWM transition, the system achieves effective output voltage stabilization without requiring a larger capacitor, thus avoiding increased device complexity and cost
Data Source
AI summary
A dual mode modulator is proposed for driving a power output stage having a serial connection of high-side power FET and low-side power FET. The dual mode modulator includes a PWM modulator operating under a PWM-frequency and a PFM modulator for controlling the power output stage. To improve the dynamic load regulation of the dual mode modulator, a dynamic frequency booster can be added to the dual mode modulator to boost up the PWM-frequency from its normal operating frequency during a PFM-to-PWM mode transition period. Secondly, a dynamic slew rate booster can be added to boost up an error amplifier slew rate of the PWM modulator from its normal operating slew rate during the mode transition period. Thirdly, a dynamic turn-off logic circuit can be added to turn off the low-side power FET during the mode transition period.