Multi-mode Redundancy Removal for Integrated Circuit Design Optimization
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Solution Overview
Problem
Existing redundancy removal techniques face significant runtime challenges in complex designs, leading to potential runtime explosions and quality of result (QoR) losses, especially when dealing with large and complex integrated circuit designs.
Innovation Solution
A multi-mode redundancy removal method that combines full-scale redundancy removal with localized redundancy removal, utilizing temporary outputs and adjustable logic depth in fan-out cones to optimize design efficiency, allowing for significant runtime improvements while maintaining QoR by leveraging the results of conventional redundancy removal techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If full-scale redundancy removal is performed on complex designs, then optimization quality is improved, but runtime increases significantly leading to runtime explosion
Solution Approach 1:
The patent segments the redundancy removal process into two distinct modes: full-scale redundancy removal for comprehensive optimization and localized redundancy removal for efficient processing. Full-scale removal analyzes the entire design to ensure high optimization quality, while localized removal focuses on specific regions or circuits, allowing the system to handle complex designs by dividing the problem into manageable segments and selecting appropriate modes based on design characteristics
Solution Approach 2:
The patent applies partial action by implementing localized redundancy removal that processes only specific portions of a design rather than the entire design. This partial processing approach reduces runtime significantly while maintaining acceptable optimization quality for targeted regions, allowing the system to achieve sufficient optimization without the excessive runtime cost of complete full-scale analysis
2Loss of time
If dynamic simulation is used to avoid proof engine, then runtime is reduced, but simulation performance is quadratic and may fail to prove redundancy
Solution Approach 1:
The patent implements a dynamic mode selection mechanism that adapts between full-scale and localized redundancy removal based on design characteristics and complexity. This dynamic approach allows the system to switch strategies: using full-scale removal when time permits and optimization quality is critical, and switching to localized removal when runtime constraints are tighter, thereby dynamically balancing runtime efficiency with optimization effectiveness
3Loss of time
If partitioning or logic windows are created to improve redundancy removal, then runtime is reduced, but optimization quality suffers unacceptable loss
Solution Approach 1:
The patent applies local quality by implementing localized redundancy removal that tailors the analysis depth and scope to specific regions of the design. Instead of uniform partitioning that sacrifices quality, the system applies appropriate analysis intensity locally: full-scale analysis for critical regions where quality is paramount, and localized analysis for less critical regions where runtime efficiency is more important, thereby maintaining overall optimization quality while reducing total runtime
Data Source
AI summary
A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the full-scale redundancy removal and the localized redundancy removal can be output.