Multi-mode Scheduler for Clock Tree Synthesis Skew Balancing
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Solution Overview
Problem
Conventional clock tree synthesis techniques face challenges in creating high-quality, skew-balanced clock trees across multiple modes in integrated circuit designs due to increasing complexity and size, often resulting in poor quality or excessive area and power overhead.
Innovation Solution
A multi-mode scheduler for clock tree synthesis that traverses clock trees across different clocks and modes, creating a task queue with specific tasks for the CTS engine to synthesize and balance clock trees while considering balancing requirements across all modes and clocks, allowing parallel processing of tasks at the same traversal level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional clock tree synthesis techniques are used, then the synthesis process can be completed, but the quality of skew-balanced clock trees deteriorates across multiple modes
Solution Approach 1:
The patent segments the clock tree synthesis process into mode-specific traversal tasks. Each mode is processed separately with dedicated skew balancing operations, allowing high-quality skew control for each mode while maintaining overall multi-mode compatibility. The clock tree is divided into mode-specific sub-trees that can be optimized independently.
Solution Approach 2:
The patent implements dynamic task queue management where the synthesis process adapts to different modes. The scheduler dynamically adjusts traversal levels, task priorities, and skew balancing parameters based on the specific mode being processed, enabling optimal performance across varying operational requirements.
2Productivity
If conventional clock tree synthesis techniques are used, then the synthesis process can be completed, but the convergence issues increase
Solution Approach 1:
The patent performs preliminary traversal and marking of clock gates with traversal levels before the actual synthesis begins. This preliminary action establishes a structured task queue that guides the synthesis process, ensuring reliable convergence by pre-planning the synthesis sequence and identifying all necessary operations in advance.
Solution Approach 2:
The patent implements feedback mechanisms where the scheduler monitors synthesis progress across different modes and adjusts task execution accordingly. The system uses traversal level information and mode-specific requirements to dynamically adjust the synthesis process, ensuring convergence reliability while maintaining productivity.
3Manufacturing precision
If conventional clock tree synthesis techniques are used, then the synthesis process can be completed, but the area and power overhead increases
Solution Approach 1:
The patent applies local quality optimization by performing skew balancing only where necessary for each specific mode. Instead of uniformly applying skew control across the entire clock tree, the system identifies mode-specific critical paths and applies balancing operations locally, reducing unnecessary area overhead while maintaining high skew balancing quality.
Solution Approach 2:
The patent implements partial action by selectively applying skew balancing to only those portions of the clock tree that require it for specific modes. The task queue system enables partial optimization where full skew balancing is applied only when necessary, avoiding excessive area overhead in regions where simple routing suffices.
4Manufacturing precision
If conventional clock tree synthesis techniques are used, then the synthesis process can be completed, but the power overhead increases
Solution Approach 1:
The patent reduces power overhead by applying skew balancing operations locally only where needed for each mode. The mode-specific traversal approach identifies critical regions requiring power-consuming balancing operations, while leaving non-critical regions with simpler, lower-power routing, thus maintaining skew quality while minimizing overall power consumption.
Solution Approach 2:
The patent implements partial skew balancing that avoids excessive power consumption. By using the task queue to selectively apply balancing operations only to necessary regions and modes, the system achieves high skew balancing quality without the excessive power overhead that would result from applying full balancing across the entire clock tree.
Data Source
AI summary
Techniques and systems for performing clock tree synthesis (CTS) across multiple modes are described. Some embodiments traverse one or more clock trees from the root of each clock tree to a set of sinks of the clock tree. During the traversal, each clock gate can be marked with a traversal level, and each sink can be marked with one or more clocks and one or more modes that are associated with the sink. A task queue can then be created based on the information collected during the clock tree traversal and populated with different types of tasks based on skew balancing requirements across different modes, and the task queue can be provided to a CTS engine to achieve high-quality skew-balanced clock trees across all modes.