Multi-Module Memory Controller for Flash Channel Parallelism
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Solution Overview
Problem
All flash array (AFA) servers face delays in read/write operations due to busy times of flash memory chips and increased demand for higher transfer rates with updated PCIe versions, leading to inefficiencies in accessing SSDs.
Innovation Solution
A memory controller architecture with multiple channels, each comprising flash memory chips, and a flash translation layer with independent control modules, command queues, and a DMA engine to manage and prioritize commands, ensuring efficient access and handling of multiple read/write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple read/write operations are performed on flash memory chips, then the transfer rate and productivity are improved, but the flash memory chips cannot perform operations during busy time, causing delays and loss of time
Solution Approach 1:
The memory controller is divided into multiple independent control modules (CM0-CM7), each capable of independently managing flash memory chip operations. This segmentation allows parallel processing of read/write commands across different channels, enabling the system to initiate new operations while previous operations are still in busy time, thereby improving productivity without being constrained by individual chip busy periods
Solution Approach 2:
The patent introduces a multi-dimensional architecture with multiple channels (CH0-CH7) and control modules operating in parallel. By transitioning from a single-channel sequential processing model to a multi-channel parallel processing model, the system can perform operations across different dimensional spaces simultaneously, effectively bypassing the time loss associated with single-chip busy periods
2Productivity
If the number of control modules is increased to handle more commands in parallel, then the productivity and bandwidth are improved, but the device complexity increases
Solution Approach 1:
Each control module is designed as a universal, multi-functional unit that can handle various types of commands (read, write, erase) across multiple flash memory chips within its assigned channel. The control modules share common functional blocks including command queues, arbiter, and DMA engines, allowing them to perform multiple functions while maintaining a standardized design that reduces overall system complexity
Solution Approach 2:
The system uses parameter-based configuration where control modules are assigned to specific channels and flash memory chips through programmable parameters rather than hardwired connections. The arbiter and command queue structures use configurable parameters to manage multiple modules, allowing the system to scale productivity by changing operational parameters rather than fundamentally redesigning the architecture
Data Source
AI summary
The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.