Multi-Modulus Frequency Divider for Near-50% Clock Duty Cycle
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi modulus frequency dividers suffer from an ideal duty cycle of their output clock signal, which affects power consumption and stability, as the duty cycle deviates significantly from 50% due to an imbalance in high and low levels of the output clock signal.
Innovation Solution
A multi modulus frequency divider is designed with a cascade connection of frequency division units, a clock output circuit, and a duty cycle adjusting circuit. Each frequency division unit includes D flip-flops and a combinational logic unit, with the clock output circuit generating a first output clock signal based on state outputs, and the duty cycle adjusting circuit generating a second output clock signal with a different duty cycle by triggering the falling edge with an input modulus signal, maintaining the same frequency as the first output clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If frequency division ratios are arbitrarily switched using extension-stage circuits in the prior art, then the multi modulus frequency divider can operate normally with wide division range, but the duty cycle of the output clock signal deviates significantly from 50% and becomes non-ideal
Solution Approach 1:
The patent segments the frequency division function into multiple independent frequency division units (first, second, and third frequency division units), each capable of independent frequency division by N or N+1. This segmentation allows arbitrary frequency division ratio switching while maintaining proper duty cycle through coordinated operation of the units, resolving the contradiction between versatility and duty cycle accuracy.
Solution Approach 2:
The patent introduces a duty cycle adjusting circuit as an intermediary component that receives the first output clock signal and generates a second output clock signal with optimized duty cycle. This intermediary circuit corrects the non-ideal duty cycle produced by the frequency division units, resolving the contradiction between frequency division flexibility and duty cycle precision.
2Reliability
If the duty cycle of the output clock signal is optimized to be close to 50%, then power consumption and stability are improved, but the complexity of the circuit increases due to additional duty cycle adjusting circuits
Solution Approach 1:
The patent optimizes the duty cycle by changing the timing parameters of the output clock signal edges. The duty cycle adjusting circuit modifies the rising and falling edge timing to achieve approximately 50% duty cycle, which improves reliability and reduces power consumption while adding minimal complexity through parameter optimization rather than structural complexity.
Solution Approach 2:
The frequency division units are designed with multi-functionality, serving both frequency division and duty cycle adjustment purposes. The same circuit blocks that perform frequency division also contribute to duty cycle optimization through their coordinated operation, reducing the need for completely separate duty cycle adjustment circuits and thereby limiting the increase in overall circuit complexity.
Data Source
AI summary
The present disclosure provides a multi modulus frequency divider and an electronic device. The duty cycle adjusting circuit in the multi modulus frequency divider is configured to generate a second output clock signal according to a first output clock signal and an input modulus signal received by one or more frequency division units, the frequency of the second output clock signal is the same as that of the first output clock signal, and the duty cycle of the second output clock signal is different from that of the first output clock signal. The duty cycle of the clock signal output by the multi modulus frequency divider provided in the present disclosure is generally closer to 50%.