Multi-Modulus Divider for Selectable Frequency and Duty Cycle
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Solution Overview
Problem
Conventional phase locked loop systems face challenges in generating high-speed digital clock signals with selectable frequencies and duty cycles, as existing dividers often produce undesirable harmonic frequencies and cannot conveniently generate required frequencies or duty cycles, especially in digital circuitry.
Innovation Solution
A multi-modulus divider that dynamically selects division ratios such as 0.75, 0.875, 1, 1.125, and 1.25 by controlling the phases of a reference frequency, combined with fixed ratio dividers to achieve division ratios like 6, 7, 8, 9, and 10, allowing for the generation of a wide range of digital clock frequencies and duty cycles using serially-connected shift registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional dividers are used to generate clock signals, then frequency division can be achieved, but undesirable harmonic frequencies are generated and the ability to conveniently generate required frequencies and duty cycles is limited
Solution Approach 1:
The patent implements a dynamic divider that can switch between different division ratios (N=2,3,4,5,6,7,8,9,10) based on control signals. This dynamic reconfigurability allows the system to adapt to different frequency requirements while maintaining clean output by selecting optimal division ratios, thereby resolving the contradiction between versatility and harmonic generation.
Solution Approach 2:
The invention changes the division ratio parameter dynamically through control logic that selects from multiple preset division ratios. By adjusting this key parameter based on the desired output frequency and duty cycle, the system can generate a wide range of frequencies without producing harmful harmonics, as each division ratio is optimized for specific frequency ranges.
2Adaptability or versatility
If pulse-swallowing technique is used to obtain desired division ratios, then non-integer and odd-integer ratios can be obtained, but the technique may generate undesirable harmonic frequencies components and may not conveniently generate every required frequency
Solution Approach 1:
The patent segments the frequency division function into multiple parallel paths, each dedicated to a specific division ratio (N=2 through N=10). Each path contains dedicated logic that cleanly divides the input frequency by its designated ratio without the need for pulse-swallowing techniques. This segmentation eliminates harmonic generation while maintaining the ability to select any required division ratio.
3Speed
If analog-to-digital converters are used to generate high speed digital clock, then conversion can be performed, but the converters are too slow to generate high speed digital clock
Solution Approach 1:
The patent replaces the mechanical/electronic analog-to-digital conversion process with a purely digital logic-based frequency division system. Instead of using slow ADCs to convert analog VCO outputs, the invention uses synchronous digital dividers that operate at the same high frequency as the input clock, thereby eliminating the speed bottleneck while maintaining the ability to generate high-speed digital clock signals with selectable frequencies and duty cycles.
Data Source
AI summary
A system and method are provided for controlling the duty cycle and frequency of a digitally generated clock. The method accepts a first clock signal having a fixed first frequency. A frequency control word with a first pattern is loaded into a first plurality of serially-connected registers. A duty cycle control word with a second pattern is loaded into a second plurality of serially-connected registers. A register clock signal is generated in response to the first clock and the first pattern. Then, a digital clock signal is generated having a frequency and duty cycle responsive to the register clock signal and the second pattern.