Multi-Modulus Divider State Control for Stable PLL Lock
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Solution Overview
Problem
Conventional multi-modulus dividers (MMDs) fail to accurately reduce signal frequencies when divisor values cross unstable division range boundaries, leading to PLL lock loss and instability.
Innovation Solution
Implementing a control circuit that changes the divisor value only during a state common to all possible divisor values, preventing the MMD from entering unknown states and ensuring accurate frequency division across division range boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the divisor value is changed during any state, then the frequency division can be adjusted to different values, but the MMD may enter unknown states causing instability and PLL lock loss
Solution Approach 1:
The control circuit is designed to only allow divisor value changes during the common state, which is predetermined and known to be safe for all divisor values. This preliminary restriction prevents the MMD from entering unknown states while still allowing flexible frequency division adjustment when the system is in the correct state.
Solution Approach 2:
The control circuit monitors the current state of the MMD and only permits divisor value changes when the common state is detected. This feedback mechanism ensures that divisor adjustments are made at the appropriate moment, preventing instability and maintaining PLL lock while allowing adaptability in frequency division ratios.
2Adaptability or versatility
If the divisor value changes across division range boundaries, then the frequency division ratio can be extended, but the MMD becomes unstable and loses PLL lock
Solution Approach 1:
The system prepares for division range boundary crossings by restricting divisor value changes to occur only during the common state, which is established beforehand as a safe transition point. This preliminary constraint allows the MMD to stably operate across extended division ranges without entering unknown states.
Solution Approach 2:
The control circuit continuously monitors the MMD state and dynamically controls when divisor value changes are permitted. This feedback ensures that even when crossing division range boundaries, the divisor is only changed during the common state, maintaining stability while enabling extended frequency division coverage.
3Adaptability or versatility
If the MMD operates with multiple divisor values, then the PLL can generate LO signals at multiple frequencies, but changing divisor values may cause unknown state transitions
Solution Approach 1:
The common state is predetermined and established before operation as a safe state for all possible divisor values. By restricting divisor changes to this pre-established state, the system ensures accurate frequency division across multiple frequencies without risking unknown state transitions or precision errors.
Solution Approach 2:
The control circuit uses feedback to detect when the MMD is in the common state before allowing divisor value changes. This ensures that transitions between different frequency generation modes occur only when the system is in a known, stable state, maintaining both accuracy and versatility in frequency generation.
Data Source
AI summary
Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include determining a common state for the MMD, wherein the MMD is configured to enter the common state regardless of a divisor value applied to the MMD. The method may further include receiving an integer value at the MMD. Further, the method may include setting the divisor value equal to the integer value. The method may also include receiving an input signal at a first frequency and generating an output signal at a second, lower frequency based on the divisor value. The method may also include receiving a second integer value at the MMD. The method may further include setting the divisor value equal to the second integer value in response to a detected current state of the MMD matching the common state for the MMD.