Multi-Nanosheet Transistor Layout With Region-Specific Gate Widths
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling and performance due to limitations in transistor design, particularly in the arrangement and configuration of active patterns, gate structures, and source/drain patterns, which affect current control and reliability.
Innovation Solution
The semiconductor device incorporates a substrate with distinct regions featuring specific active patterns, gate structures, and source/drain patterns, including multiple sheet patterns and gate electrodes, where the number and arrangement of sheet patterns differ between regions, and the gate electrodes' width and insulating film thickness are optimized to enhance current control and reduce short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of sheet patterns is increased to improve device density, then the device density improves, but the manufacturing complexity increases
Solution Approach 1:
The channel region is segmented into multiple thin-sheet patterns stacked vertically, transforming a single-channel device into a multi-channel device. This segmentation increases the effective channel width and device density without requiring a proportional increase in planar area, thereby improving density while managing manufacturing complexity through vertical stacking rather than lateral expansion.
Solution Approach 2:
The invention transitions from a two-dimensional planar channel structure to a three-dimensional stacked structure by forming multiple thin-sheet patterns in the vertical direction. This dimensional change allows the device to achieve higher density by utilizing the vertical dimension, effectively increasing the channel width without increasing the footprint area, thus resolving the contradiction between density and manufacturing complexity.
2Reliability
If different gate electrode widths are used for different active patterns, then the performance optimization for different regions improves, but the device complexity increases
Solution Approach 1:
Different gate electrode widths are assigned to different active patterns (first and second active patterns) based on their specific performance requirements. The first gate electrode has a different width than the second gate electrode, allowing each region to be optimized for its intended function (e.g., logic vs. memory operations). This local differentiation improves performance optimization while maintaining a relatively simple overall structure by only varying the gate width parameter rather than introducing fundamentally different structures.
Data Source
AI summary
A semiconductor device includes a substrate including first and second regions; a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern, a height of the second lower pattern being identical to a height of the first lower pattern, and second sheet patterns; a first gate structure including a first gate insulating film and a first gate electrode; a second gate structure including a second gate insulating film, and a second gate electrode, a width of the second gate electrode being greater than a width of the first gate electrode; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a number of first sheet patterns is smaller than a number of second sheet patterns.