Multi-operand Floating Point Addition Without Normalization
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Solution Overview
Problem
Existing floating point arithmetic operations in programmable integrated circuit devices require frequent normalization, which is resource-intensive and leads to latency issues, especially when handling multiple operands, as they must maintain the IEEE754-1985 standard's requirement of a leading '1' in mantissa representation.
Innovation Solution
A method is implemented to configure programmable integrated circuit devices to perform floating point addition on multiple operands without normalization, using a compressor and carry-propagate adder to combine shifted mantissas, allowing for simultaneous operation on multiple numbers and reducing the need for continuous normalization, thereby minimizing resource usage and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequent normalization is performed to maintain IEEE754-1985 compliance, then floating point operation accuracy is improved, but resource consumption and latency increase
Solution Approach 1:
The patent applies preliminary action by finding the maximum exponent among all operands before performing the addition operation. This preliminary step allows the system to determine the appropriate shift amount for each operand in advance, eliminating the need for repeated normalization checks during the computation process. The exponent comparison logic and shift amount calculation are performed once at the beginning, enabling subsequent direct mantissa addition without iterative normalization.
Solution Approach 2:
The patent extracts the normalization requirement from the critical path of the floating point addition operation. By separating the exponent comparison and shift amount determination as preliminary steps, the actual addition operation can proceed without waiting for normalization to be completed. This extraction of the normalization step from the main computation flow reduces latency while maintaining accuracy through the use of shift registers that preserve precision.
2Reliability
If normalization is performed continuously to maintain leading '1' representation, then IEEE754-1985 standard compliance is improved, but circuit complexity and resource usage increase
Solution Approach 1:
The patent applies partial action by performing normalization only when necessary - specifically, only the maximum exponent operand requires shift adjustment, while other operands are shifted by the difference between their exponent and the maximum exponent. This partial normalization approach maintains IEEE754 compliance without requiring continuous or excessive normalization of all operands, thereby reducing circuit complexity while preserving standard compliance.
Solution Approach 2:
The patent changes the parameter representation by using shift registers to maintain mantissa values without forcing them into normalized form with leading '1'. The system allows mantissas to be represented in their original form and uses exponent differences to control the final result scaling. This parameter change approach maintains IEEE754 compliance through the exponent field while avoiding the circuit complexity of continuous mantissa normalization.
3Measurement precision
If multiple operands are processed sequentially with normalization, then computational accuracy is maintained, but processing speed and productivity decrease
Solution Approach 1:
The patent merges multiple floating point addition operations into a single parallel processing stage. By finding the maximum exponent among all operands once and using that to determine shift amounts for all other operands simultaneously, the system can process multiple operands in parallel rather than sequentially. The compressor circuit then combines all shifted mantissas in a single operation, achieving both high computational accuracy and improved processing speed for multi-operand additions.
Data Source
AI summary
A programmable logic device is programmed to add a plurality N of unnormalized numbers at once. Because the inputs are not normalized, they could all have different exponents. The largest exponent of the N exponents is found, and for each of the inputs, its mantissa is right-shifted at by the difference between the largest exponent and the exponent of that particular input. The N shifted mantissas are combined, optionally with sign data, in an (N+1):2 compressor to provide carry and save vectors which may be combined in a carry-propagate adder. Numbers may converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step.