Multi-Operating Region Gate Model for Static Timing Analysis

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Solution Overview

Problem

Current ECAD software tools face challenges in simulating integrated circuit designs efficiently due to increased complexity with smaller transistor channel lengths, leading to longer simulation times and delayed market entry.

Innovation Solution

A multi-operating region gate model is introduced, operating in three regions (steady-state, varying current, and asymptotic) using different current source models to simplify electrical calculations, allowing for faster delay and noise analysis by reducing the complexity of circuit cell modeling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional circuit modeling methods are used with smaller transistor channel lengths, then circuit functionality and number of circuits increase, but simulation time increases significantly

Engineering Contradiction:
Improvecircuit functionalityVSAvoidsimulation time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the gate operation into three distinct operating regions (steady-state region, varying current region, and asymptotic region) and models each region with appropriate current source characteristics. This segmentation allows the complex gate behavior to be broken down into manageable portions that can be simulated more efficiently, reducing overall simulation time while maintaining accuracy for increasingly complex circuits

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the modeling parameters dynamically based on the operating region. Different current source models are used for different regions: simple current sources for steady-state, time-varying voltage-dependent current sources for varying current region, and time-invariant voltage-dependent current sources for asymptotic region. This parameter adaptation enables efficient simulation across all operating conditions

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If detailed circuit modeling is used to ensure accuracy, then timing analysis precision improves, but computational resources and simulation time increase

Engineering Contradiction:
Improvetiming analysis precisionVSAvoidsimulation speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent applies different levels of modeling detail to different operating regions based on local requirements. The steady-state region uses simple current sources where high detail is unnecessary, while the varying current region uses more complex time-varying current sources where accuracy is critical. This local quality approach ensures timing analysis precision where needed while reducing computational effort where simple models suffice

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent dynamically selects the appropriate current source model based on the instantaneous operating conditions of the gate. The model transitions between different current source characteristics as the gate moves between operating regions, providing accurate timing analysis during critical transitions while using simpler models during stable states to maintain simulation speed

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8302046B1Compact modeling of circuit stages for static timing analysis of integrated circuit designs
Publication Date: 2012.10.30 CADENCE DESIGN SYST INC
  • US8302046B1 patent drawing
  • US8302046B1 patent drawing
  • US8302046B1 patent drawing

AI summary

Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.