Multi-Order Hold RF DAC for Image Suppression at Low Sampling Rates
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Solution Overview
Problem
RF circuitry in wireless communications devices face challenges with image suppression and power consumption due to digital-to-analog conversion, particularly in devices with low RF bandwidths like Bluetooth and IoT devices, where increasing sampling frequency is not feasible.
Innovation Solution
A digital transmitter employs a multi-order hold DAC with multiple DACs and reference voltage generators to suppress or eliminate images in the RF output, operating at a low sampling frequency equal to or less than the carrier frequency, reducing power consumption and complexity by eliminating components like mixers and amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling frequency of the DAC is increased to suppress images in the RF output, then the image suppression performance is improved, but the power consumption increases
Solution Approach 1:
The patent divides the single high-order hold DAC into multiple lower-order hold DACs (e.g., two zero-order hold DACs) that operate at a lower sampling frequency. Each DAC handles a portion of the signal, and their outputs are combined to achieve the desired image suppression performance without requiring each individual DAC to operate at high sampling frequencies, thus reducing overall power consumption.
Solution Approach 2:
The patent combines the outputs of multiple DACs with different hold orders or different reference voltage variations to achieve the equivalent performance of a single high-order hold DAC. By merging the outputs of multiple lower-frequency DACs, the system achieves the same image suppression effect as a high sampling frequency DAC would provide, but with reduced power consumption.
2Measurement precision
If the sampling frequency of the DAC is increased to suppress images, then the image suppression performance is improved, but the device complexity increases
Solution Approach 1:
The patent segments the complex high-order hold DAC into multiple simpler lower-order hold DACs. Each segmented DAC has reduced complexity compared to the original high-order hold DAC, and they operate at manageable sampling frequencies. The segmentation approach makes the overall system more implementable while achieving the desired performance.
Solution Approach 2:
The patent changes the parameters of the DAC system by using multiple DACs with different hold orders (e.g., combining zero-order hold DACs instead of using a single high-order hold DAC). This parameter change allows the system to achieve the same image suppression performance with simpler individual components and lower sampling frequencies, thereby reducing overall device complexity.
3Measurement precision
If a single high-order hold DAC is used to suppress images, then the image suppression performance is improved, but the device complexity increases
Solution Approach 1:
The patent segments the single complex high-order hold DAC into multiple simpler lower-order hold DACs. This segmentation replaces one complex component with multiple simpler components that are easier to implement and manage, while maintaining the same image suppression performance through their combined output.
Solution Approach 2:
The patent changes the system parameters by transitioning from a single high-order hold DAC to multiple lower-order hold DACs with different reference voltage characteristics. This parameter transformation achieves the same performance goal with simpler individual components, reducing the complexity of each DAC unit in the system.
Data Source
AI summary
Certain aspects of the present disclosure provide a radio frequency (RF) digital transmitter. An example a RF transmitter includes a multi-order hold digital-to-analog converter (DAC) configured to output a signal with a carrier frequency in a radio frequency (RF) bandwidth, the multi-order hold DAC comprising: a first DAC and a second DAC. The RF transmitter further includes one or more reference voltage generators coupled to the multi-order hold DAC, wherein the one or more reference voltage generators are configured to feed a first reference voltage to the first DAC and feed a second reference voltage to the second DAC, and wherein the one or more reference voltage generators are configured to output the first reference voltage with a first time-varying voltage across a symbol period.