Multi-Orientation Channel Layers for Short-Channel Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices leads to a short channel effect and challenges in optimizing carrier mobility, which affects the performance of transistors.
Innovation Solution
A semiconductor device is designed with multiple channel layers having different crystallographic orientations and thicknesses, where the first channel layers have a (100) orientation and the second channel layers have a (110) orientation, surrounded by respective gate electrodes, to optimize carrier mobility in NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is miniaturized to achieve high integration, then device density increases, but short channel effect occurs and carrier mobility deteriorates
Solution Approach 1:
The patent applies local quality by assigning different crystallographic orientations to different channel layers: first channel layers have (100) orientation optimized for electron mobility in NMOS transistors, while second channel layers have (110) orientation optimized for hole mobility in PMOS transistors. This localized optimization of material properties in different regions resolves the contradiction by maintaining high carrier mobility even as transistor dimensions are reduced for higher integration density.
Solution Approach 2:
The patent employs composite materials by stacking multiple channel layers with different crystallographic orientations ((100) and (110) planes) to create a composite semiconductor structure. This composite approach allows simultaneous optimization for both electron and hole transport, addressing the performance deterioration that occurs with simple miniaturization while maintaining high device integration.
2Ease of manufacture
If single crystal orientation is used in channel layer, then manufacturing process is simple, but carrier mobility cannot be optimized for both NMOS and PMOS transistors
Solution Approach 1:
The patent implements local quality by creating regions with different crystallographic orientations within the channel structure. The first channel layers use (100) orientation for NMOS optimization while second channel layers use (110) orientation for PMOS optimization. This allows each region to have tailored properties for its specific function while using standard semiconductor fabrication techniques, thus maintaining ease of manufacture while achieving high carrier mobility for both transistor types.
Solution Approach 2:
The patent applies segmentation by dividing the channel structure into multiple discrete channel layers with different orientations rather than using a single uniform orientation. This segmentation allows independent optimization of each layer for specific carrier types while maintaining compatibility with conventional manufacturing processes, resolving the contradiction between manufacturing simplicity and performance optimization.
3Reliability
If multiple channel layers with different orientations are stacked, then carrier mobility is optimized, but device structure becomes complex
Solution Approach 1:
The patent resolves the complexity issue by transitioning from a two-dimensional planar channel structure to a three-dimensional vertically stacked structure. Multiple channel layers with different orientations are stacked in the vertical dimension, allowing simultaneous optimization for both NMOS and PMOS transistors within a compact footprint. This dimensional change enables complex functionality to be achieved through vertical stacking rather than lateral expansion, managing structural complexity efficiently.
Solution Approach 2:
The patent applies the nesting principle by stacking channel layers within a vertically integrated structure where multiple functional layers are nested together. The first and second channel layers are nested in a stacked configuration, with each layer serving a specific function (NMOS or PMOS optimization). This nested arrangement consolidates multiple optimized channels into a compact vertical structure, reducing the overall device footprint while maintaining the complexity benefits of multi-orientation channels.
Data Source
AI summary
A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.