Multi-Orientation Channel Layers for Short-Channel MOSFET Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices leads to a short channel effect, and there is a need to optimize carrier mobility in channels to improve the performance of semiconductor devices.
Innovation Solution
A semiconductor device is designed with multiple channel layers having different crystallographic orientations and varying thicknesses, surrounded by gate electrodes, to optimize carrier mobility in NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is miniaturized to achieve high integration, then device density increases, but short channel effect occurs degrading device performance
Solution Approach 1:
The channel region is segmented into multiple independent channel layers (first channel layers and second channel layers) with different crystallographic orientations. This segmentation allows each layer to contribute differently to carrier transport, enabling high integration density while maintaining performance through the combined effect of multiple channels rather than relying on a single miniaturized channel.
Solution Approach 2:
Different regions of the semiconductor device are assigned different crystallographic orientations locally. The first channel layers have a first crystallographic orientation optimized for one type of carrier transport, while the second channel layers have a second crystallographic orientation optimized for another type. This local quality differentiation allows simultaneous optimization of performance in different regions despite overall miniaturization.
2Speed
If channel thickness is reduced to improve switching speed, then operating frequency increases, but carrier mobility decreases due to increased scattering
Solution Approach 1:
The crystallographic orientation parameter is changed between different channel layers. By using different crystal orientations (e.g., <100> vs <110>), the patent exploits the anisotropic nature of carrier mobility in semiconductors to maintain high mobility even in thin channels. Each orientation has different mobility characteristics that can be optimized for specific operating conditions.
Solution Approach 2:
The channel region is constructed as a composite structure with multiple channel layers having different crystallographic orientations. This composite channel structure combines the advantages of different orientations, achieving both high-speed operation and high carrier mobility that cannot be obtained with a single uniform channel structure.
3Reliability
If multiple channel layers with different orientations are introduced to optimize carrier mobility, then device performance improves, but device structure becomes more complex
Solution Approach 1:
Multiple channel layers with different crystallographic orientations are merged into a single integrated channel structure. The first channel layers and second channel layers are combined within the same semiconductor device, sharing common source and drain regions. This merging approach achieves performance optimization through diversity while avoiding the complexity of completely separate device structures.
Solution Approach 2:
The multi-layer channel structure serves multiple functions simultaneously: it provides high integration density, optimizes carrier mobility for different carrier types, and maintains compatibility with existing manufacturing processes. The gate electrode structure universally controls all channel layers, and the source/drain regions serve as common contacts for multiple channels, reducing overall device complexity.
Data Source
AI summary
A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.