Multi-Oscillator Clock Switching for Low-Jitter Frequency Scaling
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Solution Overview
Problem
Conventional clock generators in integrated circuits face challenges in rapidly switching between clock frequencies, leading to temporary unavailability of clock signals, jitter issues, and radio frequency interference, while also consuming excessive power due to the need for PLL stabilization and lock regeneration.
Innovation Solution
A clock generator with a pool of oscillator circuits and a multiplexing circuit allows for rapid frequency switching without stabilizing oscillators, using a frequency divider with integer division factors to minimize jitter and power consumption, and a joint voltage-frequency scaling facility to optimize power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional programmable PLL circuits are used for frequency switching, then a wide range of clock frequencies can be generated, but the clock signal becomes temporarily unavailable during frequency changes due to PLL lock regeneration
Solution Approach 1:
The patent pre-generates multiple clock signals at different frequencies using separate oscillator circuits before frequency switching is needed. These pre-generated clock signals are stored in buffer registers, allowing immediate switching without PLL lock regeneration delays, thus maintaining clock signal availability while providing wide frequency range.
Solution Approach 2:
The clock generation system is divided into multiple independent oscillator circuits, each generating a specific clock frequency. This segmentation allows any oscillator to be independently selected and switched to the multiplexer without affecting other oscillators, enabling rapid frequency switching without lock regeneration delays.
2Adaptability or versatility
If fractional division is used in PLL to provide detailed frequency selection, then a multitude of clock frequencies can be selected, but unacceptable amount of jitter is introduced
Solution Approach 1:
Instead of using fractional division in a single PLL, the patent segments the frequency generation into multiple integer-frequency oscillators. Each oscillator produces a clock signal with an integer multiple of a base frequency, eliminating fractional division and its associated jitter while still providing fine frequency granularity through the selection of multiple discrete oscillator frequencies.
3Measurement precision
If high frequencies are used to provide detailed frequency selection, then fine frequency resolution is achieved, but radio frequency interference problems occur
Solution Approach 1:
The patent changes the frequency parameter by providing multiple discrete frequency options from different oscillators (e.g., 50MHz, 100MHz, 150MHz, 200MHz) rather than using a single high frequency. This allows fine frequency resolution through selection of appropriate base frequencies and division ratios while avoiding the RF interference problems associated with continuously high frequency operation.
4Adaptability or versatility
If multiple programmable PLL circuits are used for each sub-circuit, then each sub-circuit can have independent frequency control, but power consumption increases
Solution Approach 1:
The patent merges multiple frequency generation functions into a single shared pool of oscillator circuits that serves all sub-circuits. A multiplexer routes the appropriate pre-generated clock signals to different sub-circuits as needed, eliminating the need for multiple independent PLL circuits and significantly reducing overall power consumption while maintaining independent frequency control capability for each sub-circuit.
Solution Approach 2:
The oscillator pool is designed as a universal resource that can generate clock signals for any sub-circuit. The multiplexer enables any oscillator to serve any sub-circuit, making the system multi-functional and eliminating redundant circuitry, thereby reducing power consumption while preserving independent frequency control.
Data Source
AI summary
A data processing system comprises a plurality of sub-circuits, a clock generator provided with a control circuit, a pool of oscillator circuits comprising at least three oscillator circuits, and a multiplexing circuit coupled between the pool and clock inputs of the sub-circuits. The multiplexing circuit has a control input coupled to a control output of the control circuit. The multiplexing circuit is configured to couple any selectable one of the oscillator circuits in the pool to a clock input of each of the sub-circuits. The control circuit is configured to set the frequencies of respective ones of the clock circuit by controlling the multiplexing circuit to supply clock signals derived from selected ones of the oscillator circuits to the sub-circuits.